Thin film magnetic memory device including memory cells having a magnetic tunnel junction

ABSTRACT

In the data read operation, a memory cell and a dummy memory cell are respectively coupled to two bit lines of a selected bit line pair, and a data read current is supplied thereto. In the selected memory cell column, a read gate drives the respective voltages on a read data bus pair, according to the respective voltages on the bit lines. A data read circuit amplifies the voltage difference between the read data buses so as to output read data. The use of the read gate enables the read data buses to be disconnected from a data read current path. As a result, respective voltage changes on the bit lines are rapidly produced, whereby the data read speed can be increased.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a thin film magnetic memorydevice. More particularly, the present invention relates to a randomaccess memory (RAM) including memory cells having a magnetic tunneljunction (MTJ).

[0003] 2. Description of the Background Art

[0004] An MRAM (Magnetic Random Access Memory) device has attractedattention as a memory device capable of non-volatile data storage withlow power consumption. The MRAM device is a memory device that storesdata in a non-volatile manner using a plurality of thin film magneticelements formed in a semiconductor integrated circuit and is capable ofrandom access to each thin film magnetic element.

[0005] In particular, recent announcement shows that significantprogress in performance of the MRAM device is achieved by using thinfilm magnetic elements having a magnetic tunnel junction (MTJ) as memorycells. The MRAM device including memory cells having a magnetic tunneljunction is disclosed in technical documents such as “A 10 ns Read andWrite Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FETSwitch in each Cell”, ISSCC Digest of Technical Papers, TA7.2, February2000, and “Nonvolatile RAM based on Magnetic Tunnel Junction Elements”,ISSCC Digest of Technical Papers, TA7.3, February 2000.

[0006]FIG. 83 is a schematic diagram showing the structure of a memorycell having a magnetic tunnel junction (hereinafter, also simplyreferred to as “MTJ memory cell”).

[0007] Referring to FIG. 83, the MTJ memory cell includes a magnetictunnel junction MTJ whose resistance value varies according to thestorage data level, and an access transistor ATR. The access transistorATR is formed from a field effect transistor, and is coupled between themagnetic tunnel junction MTJ and the ground voltage Vss.

[0008] For the MTJ memory cell are provided a write word line WWL forinstructing a data write operation, a read word line RWL for instructinga data read operation, and a bit line BL serving as a data line fortransmitting an electric signal corresponding to the storage data levelin the data read and write operations.

[0009]FIG. 84 is a conceptual diagram illustrating the data readoperation from the MTJ memory cell.

[0010] Referring to FIG. 84, the magnetic tunnel junction MTJ has amagnetic layer FL having a fixed magnetic field of a fixed direction(hereinafter, also simply referred to as “fixed magnetic layer FL”), anda magnetic layer VL having a free magnetic field (hereinafter, alsosimply referred to as “free magnetic layer VL”). A tunnel barrier TBformed from an insulator film is provided between the fixed magneticlayer FL and the free magnetic layer VL. According to the storage datalevel, either a magnetic field of the same direction as that of thefixed magnetic layer FL or a magnetic field of the direction differentfrom that of the fixed magnetic layer FL has been written to the freemagnetic layer VL in a non-volatile manner.

[0011] In reading the data, the access transistor ATR is turned ON inresponse to activation of the read word line RWL. As a result, a sensecurrent Is flows through a current path formed by the bit line BL,magnetic tunnel junction MTJ, access transistor ATR and ground voltageVss. The sense current Is is supplied as a constant current from anot-shown control circuit.

[0012] The resistance value of the magnetic tunnel junction MTJ variesaccording to the relative relation of the magnetic field directionbetween the fixed magnetic layer FL and the free magnetic layer VL. Morespecifically, in the case where the fixed magnetic layer FL and the freemagnetic layer VL have the same magnetic field direction, the magnetictunnel junction MTJ has a smaller resistance value as compared to thecase where both magnetic layers have different magnetic fielddirections.

[0013] Accordingly, in the data read operation, a voltage changeproduced at the magnetic tunnel junction MTJ due to the sense current Isvaries according to the magnetic field direction stored in the freemagnetic layer VL. Thus, by starting supply of the sense current Is withthe bit line BL precharged to a high voltage, the storage data level inthe MTJ memory cell can be read by monitoring a voltage level change onthe bit line BL.

[0014]FIG. 85 is a conceptual diagram illustrating the data writeoperation to the MTJ memory cell.

[0015] Referring to FIG. 85, in the data write operation, the read wordline RWL is inactivated, and the access transistor ATR is turned OFF. Inthis state, a data write current for writing a magnetic field to thefree magnetic layer VL is applied to the write word line WWL and the bitline BL. The magnetic field direction of the free magnetic layer VL isdetermined by combination of the respective directions of the data writecurrent flowing through the write word line WWL and the bit line BL.

[0016]FIG. 86 is a conceptual diagram illustrating the relation betweenthe respective directions of the data write current and the magneticfield in the data write operation.

[0017] Referring to FIG. 86, a magnetic field Hx of the abscissaindicates the direction of a magnetic field H(WWL) produced by the datawrite current flowing through the write word line WWL. A magnetic fieldHy of the ordinate indicates the direction of a magnetic field H(BL)produced by the data write current flowing through the bit line BL.

[0018] The magnetic field direction stored in the free magnetic layer VLis updated only when the sum of the magnetic fields H(WWL) and H(BL)reaches the region outside the asteroid characteristic line shown in thefigure. In other words, the magnetic field direction stored in the freemagnetic layer VL is not updated when a magnetic field corresponding tothe region inside the asteroid characteristic line is applied.

[0019] Accordingly, in order to update the storage data of the magnetictunnel junction MTJ by the data write operation, a current must beapplied to both the write word line WWL and the bit line BL. Once themagnetic field direction, i.e., the storage data, is stored in themagnetic tunnel junction MTJ, it is held therein in a non-volatilemanner until a new data write operation is conducted.

[0020] The sense current Is flows through the bit line BL in the dataread operation. However, the sense current Is is generally set to avalue that is smaller than the above-mentioned data write current byabout one or two orders of magnitude. Therefore, it is less likely thatthe storage data in the MTJ memory cell is erroneously rewritten duringthe data read operation due to the sense current Is.

[0021] The above-mentioned technical documents disclose a technology offorming an MRAM device, a random access memory, having such MTJ memorycells integrated on a semiconductor substrate.

[0022]FIG. 87 is a conceptual diagram showing the MTJ memory cellsarranged in rows and columns in an integrated manner.

[0023] Referring to FIG. 87, with the MTJ memory cells arranged in rowsand columns on the semiconductor substrate, a highly integrated MRAMdevice can be realized. FIG. 87 shows the MTJ memory cells arranged in nrows by in columns (where n, m is a natural number).

[0024] As described before, the bit line BL, write word line WWL andread word line RWL must be provided for each MTJ memory cell.Accordingly, n write word lines WWL1 to WWLn, n read word lines RWL1 toRWLn, and in bit lines BL1 to BLm are required for the n×m MTJ memorycells.

[0025] Thus, the MTJ memory cells are generally provided with theindependent word lines for the read and write operations.

[0026]FIG. 88 is a structural diagram of the MTJ memory cell provided onthe semiconductor substrate.

[0027] Referring to FIG. 88, the access transistor ATR is formed in ap-type region PAR of the semiconductor main substrate SUB. The accesstransistor ATR has source/drain regions (n-type regions) 110, 120 and agate 130. The source/drain region 110 is coupled to the ground voltageVss through a metal wiring formed in a first metal wiring layer M1. Ametal wiring formed in a second metal wiring layer M2 is used as thewrite word line WWL. The bit line BL is provided in a third metal wiringlayer M3.

[0028] The magnetic tunnel junction MTJ is provided between the secondmetal wiring layer M2 of the write word line WWL and the third metalwiring layer M3 of the bit line BL. The source/drain region 120 of theaccess transistor ATR is electrically coupled to the magnetic tunneljunction MTJ through a metal film 150 formed in a contact hole, thefirst and second metal wiring layers M1 and M2, and a barrier metal 140.The barrier metal 140 is a buffer material for providing electricalcoupling between the magnetic tunnel junction MTJ and the metal wirings.

[0029] As described before, the MTJ memory cell is provided with theread word line RWL independently of the write word line WWL. Inaddition, in the data write operation, a data write current forgenerating a magnetic field equal to or higher than a predeterminedvalue must be applied to the write word line WWL and the bit line BL.Accordingly, the bit line BL and the write word line WWL are each formedfrom a metal wiring.

[0030] On the other hand, the read word line RWL is provided in order tocontrol the gate voltage of the access transistor ATR, and a currentneed not be actively applied to the read word line RWL. Accordingly,from the standpoint of the improved integration degree, the read wordline RWL is conventionally formed from a polysilicon layer, polycidestructure, or the like in the same wiring layer as that of the gate 130without providing an additional independent metal wiring layer.

[0031] As described in connection with FIG. 84, the data read operationof the MTJ memory cell is conducted based on the voltage change causedby the sense current (Is in FIG. 84) supplied to the magnetic tunneljunction MTJ serving as a resistive element. This voltage change cannotbe quickly produced with a large RC (resistance-capacitance) timeconstant of the sense current path, making it impossible to increase thedata read operation speed.

[0032] Moreover, as shown in FIG. 86, the data write operation isconducted based on the relation between the applied magnetic field andthe asteroid characteristic line provided as a threshold. Accordingly,variation in asteroid characteristic line as produced in manufacturingthe memory cells results in variation in data write margin to the memorycell.

[0033]FIG. 89 is a conceptual diagram illustrating the effects of themanufacturing variation on the data write margin.

[0034] Referring to FIG. 89, the design value of the asteroidcharacteristic line is denoted with ASd. It is now assumed that theasteroid characteristic line of the memory cell is deviated from thedesign value, as shown by ASa or ASb.

[0035] For example, in the MTJ memory cell having the asteroidcharacteristic line ASb, the data cannot be written even if the datawrite current according to the design value is supplied for applicationof the data write magnetic field.

[0036] On the other hand, in the MTJ memory cell having the asteroidcharacteristic line ASa, the data is written even if the data writemagnetic field smaller than the design value is applied. As a result,the MTJ memory cell having such characteristics is extremely susceptibleto the magnetic noise.

[0037] Such manufacturing variation in asteroid characteristic line mayfurther be increased as the memory cells are miniaturized for improvedintegration. Accordingly, in order to ensure the manufacturing yield,there is a need not only for development of the manufacturing technologythat reduces the manufacturing variation in asteroid characteristicline, but also for the adjustment technology for ensuring an appropriatedata write margin corresponding to the variation in asteroidcharacteristic line.

[0038] Moreover, as described in connection with FIGS. 85 and 86, arelatively large data write current must be supplied to the bit line BLand the write word line WWL in the data write operation. As the datawrite current is increased, the current density in the bit line BL andthe write word line WWL is also increased, which may possibly cause aphenomenon called electromigration.

[0039] Electromigration may cause disconnection or short-circuit of thewirings, thereby possibly degrading the operation reliability of theMRAM device. Moreover, an increased data write current may possiblyproduce a considerable amount of magnetic noise. It is thereforedesirable to realize the structure capable of writing the data with asmaller data write current.

[0040] As described in connection with FIGS. 87 and 88, a large numberof wirings are required to write and read the data to and from the MTJmemory cell, making it difficult to reduce the area of the memory arrayintegrating the MTJ memory cells, and thus the chip area of the MRAMdevice.

[0041] An MTJ memory cell using a PN junction diode as an access elementinstead of the access transistor is known as a memory cell structurecapable of achieving improved integration over the MTJ memory cell shownin FIG. 83.

[0042]FIG. 90 is a schematic diagram showing the structure of the MTJmemory cell using the diode.

[0043] Referring to FIG. 90, the MTJ memory cell using the diodeincludes a magnetic tunnel junction MTJ and an access diode DM. Theaccess diode DM is coupled between the magnetic tunnel junction MTJ andthe word line WL. Herein, the direction from the magnetic tunneljunction MTJ toward the word line WL is the forward direction. The bitline BL extending in such a direction that crosses the word line WL iscoupled to the magnetic tunnel junction MTJ.

[0044] In the MTJ memory cell using the diode, the data write operationis conducted with the data write current being supplied to the word lineWL and the bit line BL. As in the case of the memory cell using theaccess transistor, the direction of the data write current is setaccording to the write data level.

[0045] On the other hand, in the data read operation, the word line WLcorresponding to the selected memory cell is set to the low voltage(e.g., ground voltage Vss) state. By precharging the bit line BL to thehigh voltage (e.g., power supply voltage Vcc) state, the access diode DMis rendered conductive, allowing the sense current Is to be suppliedthrough the magnetic tunnel junction MTJ. The word lines WLcorresponding to the non-selected memory cells are set to the highvoltage state. Therefore, the corresponding access diodes DM areretained in the OFF state, and no sense current Is flows therethrough.

[0046] Thus, the data read and write operations can be conducted also inthe MTJ memory cell using the access diode.

[0047]FIG. 91 is a structural diagram of the MTJ memory cell of FIG. 90provided on the semiconductor substrate.

[0048] Referring to FIG. 91, the access diode DM is formed on thesemiconductor substrate SUB from an N-type region NWL formed from, e.g.,an N-type well, and a P-type region PRA formed thereon.

[0049] The N-type well NWL, which corresponds to the cathode of theaccess diode DM, is coupled to the word line WL provided in the metalwiring layer M1. The P-type region PRA, which corresponds to the anodeof the access diode DM, is electrically coupled to the magnetic tunneljunction MTJ through the barrier metal 140 and the metal film 150. Thebit line BL is provided in the metal wiring layer M2 so as to be coupledto the magnetic tunnel junction MTJ. Thus, by replacing the accesstransistor with the access diode, the MTJ memory cell that isadvantageous in terms of improvement in integration degree can beobtained.

[0050] The data write current flows through the word line WL and the bitline BL in the data write operation. This causes a voltage drop on theselines. Such a voltage drop may turn ON the PN junction of the accessdiode DM of at least one of the MTJ memory cells that are not selectedfor the data write operation. As a result, a current may unexpectedlyflow through the MTJ memory cell, causing an erroneous data writeoperation.

[0051] Thus, the conventional MTJ memory cell using the access diode isadvantageous in terms of improved integration, but is problematic inview of the stability of the data write operation.

SUMMARY OF THE INVENTION

[0052] It is an object of the present invention to increase the datawrite speed in an MRAM device including MTJ memory cells.

[0053] It is another object of the present invention to provide thestructure capable of easily adjusting the amount of data write currentso as to assure a predetermined data write margin in the MRAM deviceincluding the MTJ memory cells, by compensating for variation inmagnetic characteristics due to manufacturing variation.

[0054] It is a further object of the present invention to achieveimprovement in operation reliability as well as suppression of magneticnoise in the MRAM device including the MTJ memory cells, by reducing thedata write current.

[0055] It is a still further object of the present invention to providethe MTJ memory cell structure capable of improved integration andproviding excellent operation reliability.

[0056] It is a yet further object of the present invention to suppressthe chip area of the MRAM device including the MTJ memory cells arrangedin an array, by improving the freedom of layout as well as reducing thenumber of wirings required for the entire memory array.

[0057] In summary, according to the present invention, a thin filmmagnetic memory device includes a memory array, a plurality of first bitlines, a plurality of read word lines, a first read data line, a readgate circuit, and a data read circuit. The memory array includes aplurality of magnetic memory cells arranged in rows and columns. Each ofthe plurality of magnetic memory cells has either a first or secondresistance value according a storage data level thereof. The pluralityof first bit lines are provided corresponding to the respective columnsof the magnetic memory cells. The plurality of read word lines areprovided corresponding to the respective rows of the magnetic memorycells, for electrically coupling the magnetic memory cells correspondingto an addressed row between the plurality of first bit lines set to afirst voltage and a second voltage (Vss), respectively, so as to pass adata read current through the magnetic memory cells. The first read dataline transmits read data. The read gate circuit sets a voltage of thefirst read data line according to a voltage on one of the plurality offirst bit lines that corresponds to an addressed column. The data readcircuit sets a level of the read data according to the voltage on thefirst read data line.

[0058] Therefore, a primary advantage of the present invention is thatthe data read speed can be increased by rapidly producing a voltagechange on the first bit line by conducting the data read operation witha reduced RC constant of the data read current path, without supplyingany data read current to the first read data line.

[0059] According to another aspect of the present invention, a thin filmmagnetic memory device having a normal operation mode and a test modeincludes a memory array, a plurality of write word lines, a write wordline driver, a data write circuit, and a plurality of bit line pairs.The memory array includes a plurality of magnetic memory cells arrangedin rows and columns. Each of the plurality of magnetic memory cells hasa different resistance value according to a level of storage datawritten when a data write magnetic field applied by first and seconddata write currents is larger than a predetermined magnetic field. Theplurality of write word lines are provided corresponding to therespective rows of the magnetic memory cells, and selectively activatedaccording a row selection result in a data write operation. The writeword line driver supplies the first data write current to the activatedword line in an amount corresponding to a voltage level on a firstcontrol node. The data write circuit supplies the second data writecurrent in the data write operation in an amount corresponding to avoltage level on a second control node. The plurality of bit lines areprovided corresponding to the respective columns of the magnetic memorycells, and selectively connected to the data write circuit according toa column selection result in the data write operation. At least one ofthe write word line driver and the data write circuit includes an inputterminal for externally setting the voltage level of a corresponding oneof the first and second control nodes in the test mode.

[0060] Accordingly, in the test mode, at least one of the first andsecond data write currents can be set from the outside. Thus, themanufacturing variation in magnetic characteristics of the MTJ memorycells can be compensated for, whereby the adjustment testing of the datawrite current amount for appropriately ensuring a data write margin canbe facilitated.

[0061] According to a further aspect of the present invention, a thinfilm magnetic memory device includes a memory array, a plurality of bitlines, a plurality of write word lines, and a coupling circuit. Thememory array includes a plurality of magnetic memory cells arranged inrows and columns. Each of the plurality of magnetic memory cellsincludes a magnetic storage portion having a different resistance valueaccording to a level of storage data written when a data write magneticfield applied by first and second data write currents is larger than apredetermined magnetic field. The plurality of bit lines are providedcorresponding to the respective columns of the magnetic memory cells,for passing the first data write current therethrough. The plurality ofwrite word lines are provided corresponding to the respective rows ofthe magnetic memory cells, and selectively activated according anaddress selection result so as to pass the second data write currenttherethrough in a data write operation. Each of the write word linesincludes first and second sub write word lines respectively formed infirst and second metal wiring layers with the magnetic storage portionsinterposed therebetween in a vertical direction on a semiconductorsubstrate. The coupling circuit electrically couples the first andsecond sub write word lines to each other. The second data write currentflows as a reciprocating current through the first and second sub writeword lines electrically coupled to each other by the coupling circuit.

[0062] Thus, since the data write current flows as a reciprocatingcurrent through the first and second bit lines that are electricallycoupled to each other, data write magnetic fields acting in the samedirection can be generated in the magnetic storage portion. This reducesthe amount of data write current required to generate a data writemagnetic field of the same strength. As a result, reduced powerconsumption of the MRAM device, improved operation reliability resultingfrom the reduced current density of the bit line, and also reducedmagnetic field noise in the data write operation can be realized.

[0063] According to a still further aspect of the present invention, athin film magnetic memory device includes a memory array, a plurality ofread word lines, a plurality of write word lines, and a plurality of bitlines. The memory array includes a plurality of magnetic memory cellsarranged in rows and columns. Each of the plurality of magnetic memorycells includes a magnetic storage portion having a different resistancevalue according to a level of storage data written when a data writemagnetic field applied by first and second data write currents is largerthan a predetermined magnetic field. The plurality of read word linesare provided corresponding to the respective rows of the magnetic memorywells, and are driven to a first voltage according to a row selectionresult in a data read operation. The plurality of write word lines areprovided corresponding to the respective rows, and are selectivelyactivated according an address selection result so as to pass the firstdata write current therethrough in a data write operation. The pluralityof bit lines are provided corresponding to the respective columns of themagnetic memory cells so as to extend in such a direction that crossesthe plurality of write word lines, and are each coupled to the magneticstorage portions. One of the plurality of bit lines that is selectedaccording to an address selection result passes therethrough a data readcurrent and the second data write current in the data read operation andthe data write operation, respectively. Each of the magnetic memorycells further includes a rectifying element connected between thecorresponding magnetic storage portion and the corresponding read wordline.

[0064] Such a magnetic memory cell using the rectifying element isadvantageous in terms of improved integration, and the OFF state of therectifying element can be reliably maintained in the non-selectedmagnetic memory cells. As a result, the improved integration can beachieved as well as the operation reliability can be ensured.

[0065] According to a yet further aspect of the present invention, athin film magnetic memory device includes a memory array, a plurality ofread word lines, a plurality of write word lines, a plurality of writedata lines, and a plurality of read data lines. The memory arrayincludes a plurality of magnetic memory cells arranged in rows andcolumns. Each of the plurality of magnetic memory cells includes amagnetic storage portion having a different resistance value accordingto a level of storage data written when a data write magnetic fieldapplied by first and second data write currents is larger than apredetermined magnetic field, and a memory cell selection gate forpassing a data read current therethrough into the magnetic storageportion in a data read operation. The plurality of read word lines areprovided corresponding to the respective rows of the magnetic memorycells, for actuating the corresponding memory cell selection gateaccording to an address selection result in the data read operation. Theplurality of write word lines are provided corresponding to therespective columns of the magnetic memory cells, and are selectivelydriven to an active state according to an address selection result so asto pass the first data write current therethrough in a data writeoperation. The plurality of write data lines are provided correspondingto the respective rows, for passing the second data write currenttherethrough in the data write operation. The plurality of read datalines are provided corresponding to the respective columns, for passingthe data read current therethrough in the data read operation. Adjacentmagnetic memory cells share a corresponding one of at least one of theplurality of write word lines, the plurality of read word lines and theplurality of data lines.

[0066] Thus, the read word lines and the write word lines are providedcorresponding to the rows and columns of the magnetic memory cells,respectively, and respective circuits for selectively driving the readword lines and the write word lines are provided independently.Accordingly, the freedom of layout can be improved. Moreover, at leastone of the write word lines, read word lines, write data lines, and readdata lines are shared between corresponding adjacent memory cells,whereby a wiring pitch in the memory array can be widened. As a result,the integration degree of the MRAM device can be improved.

[0067] According to a yet further aspect of the present invention, athin film magnetic memory device includes a memory array, a plurality ofread word lines, a plurality of write data lines, a plurality of commonlines, and a current control circuit. The memory array includes aplurality of magnetic memory cells arranged in rows and columns. Each ofthe plurality of magnetic memory cells includes a magnetic storageportion having a different resistance value according to a level ofstorage data written when a data write magnetic field applied by firstand second data write currents is larger than a predetermined magneticfield, and a memory cell selection gate for passing a data read current(Is) therethrough into the magnetic storage portion in a data readoperation. The plurality of read word lines are provided correspondingto the respective rows of the magnetic memory cells, for actuating thecorresponding memory cell selection gate according to an addressselection result in the data read operation. The plurality of write datalines are provided corresponding to the respective rows, for passing thefirst data write current therethrough in a data write operation. Theplurality of common lines are provided corresponding to the respectivecolumns of the magnetic memory cells. Each of the plurality of commonlines selectively receives supply of the data read current according tothe address selection result in the data read operation. Each of theplurality of common lines is selectively driven to a first voltage (Vcc)for passing the second data write current therethrough according to theaddress selection result in the data write operation. The currentcontrol circuit electrically couples and disconnects each of the commonlines to and from a second voltage (Vss) in the data write operation andthe data read operation, respectively. The second voltage is differentfrom the first voltage. Adjacent magnetic memory cells share acorresponding one of at least one of the plurality of write data lines,the plurality of read word lines and the plurality of common lines.

[0068] Thus, each common line functions as a read data line in the dataread operation, and as a write word line in the data write operation,whereby the number of wirings can be reduced. A circuit for selectivelydriving the read word lines and a circuit for selectively driving thecommon lines in the data write operation, i.e., the common linesfunctioning as write word lines, are provided independently, whereby thefreedom of layout can be improved. Moreover, at least one of the readword lines, write data lines and common lines are shared betweencorresponding adjacent memory cells, whereby a wiring pitch in thememory array can be widened. As a result, the integration degree of theMRAM device can be improved.

[0069] The foregoing and other objects, features, aspects and advantagesof the present invention will become more apparent from the followingdetailed description of the present invention when taken in conjunctionwith the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0070]FIG. 1 is a schematic block diagram showing the overall structureof an MRAM device 1 according to a first embodiment of the presentinvention.

[0071]FIG. 2 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to the first embodiment.

[0072]FIG. 3 is a circuit diagram showing the structure of a data writecircuit 51 a of FIG. 2.

[0073]FIG. 4 is a circuit diagram showing the structure of a data readcircuit 55 a of FIG. 2.

[0074]FIG. 5 is a timing chart illustrating the data read and writeoperations in the MRAM device according to the first embodiment.

[0075]FIG. 6 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a first modification of thefirst embodiment.

[0076]FIG. 7 is a circuit diagram showing the structure of a data writecircuit 51 b of FIG. 6.

[0077]FIG. 8 is a circuit diagram showing the structure of a data readcircuit 55 b of FIG. 6.

[0078]FIG. 9 is a timing chart illustrating the data read and writeoperations in an MRAM device according to the first modification of thefirst embodiment.

[0079]FIG. 10 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a second modification ofthe first embodiment.

[0080]FIG. 11 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a third modification of thefirst embodiment.

[0081]FIG. 12 is a circuit diagram showing the structure of a data writecircuit according to a second embodiment of the present invention.

[0082]FIG. 13 is a circuit diagram showing an example of the structureof a word line driver according to the second embodiment.

[0083]FIG. 14 is a circuit diagram showing the structure of a data writecurrent adjustment circuit 230 according to a modification of the secondembodiment.

[0084]FIG. 15 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry in an MRAM device for conducting a dataread operation without using any read gate.

[0085]FIG. 16 is a block diagram illustrating the bit line arrangementaccording to a third embodiment of the present invention.

[0086]FIG. 17 is a structural diagram showing a first example of the bitline arrangement according to the third embodiment.

[0087]FIG. 18 is a structural diagram showing a second example of thebit line arrangement according to the third modification.

[0088]FIG. 19 is a conceptual diagram illustrating the bit linearrangement according to a first modification of the third embodiment.

[0089]FIG. 20 is a structural diagram illustrating the arrangement of awrite word line WWL according to a second modification of the thirdembodiment.

[0090]FIGS. 21A and 21B are conceptual diagrams illustrating thecoupling between sub-word lines forming the same write word line.

[0091]FIG. 22 is a diagram illustrating the write word line arrangementaccording to a third modification of the third embodiment.

[0092]FIG. 23 is a diagram illustrating the write word line arrangementaccording to a fourth modification of the third embodiment.

[0093]FIG. 24 is a diagram illustrating the write word line arrangementaccording to a fifth modification of the third embodiment.

[0094]FIG. 25 is a diagram showing the structure of an MTJ memory cellaccording to a fourth embodiment of the present invention.

[0095]FIG. 26 is a structural diagram of the MTJ memory cell of FIG. 25provided on a semiconductor substrate.

[0096]FIG. 27 is a timing chart illustrating the read and writeoperations from and to the MTJ memory cell of FIG. 25.

[0097]FIG. 28 is a conceptual diagram showing the structure of a memoryarray having the MTJ memory cells of FIG. 25 arranged in rows andcolumns.

[0098]FIG. 29 is a conceptual diagram showing the structure of a memoryarray in which the MTJ memory cells arranged in rows and columns sharewrite word lines WWL.

[0099]FIG. 30 is a conceptual diagram showing the MTJ memory cellarrangement according to a modification of the fourth embodiment.

[0100]FIG. 31 is a schematic block diagram showing the overall structureof an MRAM device 2 according to a fifth embodiment of the presentinvention.

[0101]FIG. 32 is a circuit diagram showing the connection of an MTJmemory cell according to the fifth embodiment.

[0102]FIG. 33 is a timing chart illustrating the data read and writeoperations from and to the MTJ memory cell according to the fifthembodiment.

[0103]FIG. 34 is a structural diagram illustrating the MTJ memory cellarrangement according to the fifth embodiment.

[0104]FIG. 35 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to the fifth embodiment.

[0105]FIG. 36 is a circuit diagram showing the structure of a data readcircuit 55 e.

[0106]FIG. 37 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a first modification of thefifth embodiment.

[0107]FIG. 38 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a second modification ofthe fifth embodiment.

[0108]FIG. 39 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a third modification of thefifth embodiment.

[0109]FIG. 40 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a fourth modification ofthe fifth embodiment.

[0110]FIG. 41 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a fifth modification of thefifth embodiment.

[0111]FIG. 42 is a circuit diagram showing the connection of an MTJmemory cell according to a sixth embodiment of the present invention.

[0112]FIG. 43 is a structural diagram illustrating the MTJ memory cellarrangement according to the sixth embodiment.

[0113]FIG. 44 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to the sixth embodiment.

[0114]FIG. 45 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a first modification of thesixth embodiment.

[0115]FIG. 46 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a second modification ofthe sixth embodiment.

[0116]FIG. 47 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a third modification of thesixth embodiment.

[0117]FIG. 48 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a fourth modification ofthe sixth embodiment.

[0118]FIG. 49 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a fifth modification of thesixth embodiment.

[0119]FIG. 50 is a circuit diagram showing the connection of an MTJmemory cell according to a seventh embodiment of the present invention.

[0120]FIG. 51 is a structural diagram showing the MTJ memory cellarrangement according to the seventh embodiment.

[0121]FIG. 52 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to the seventh embodiment.

[0122]FIG. 53 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a first modification of theseventh embodiment.

[0123]FIG. 54 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a second modification ofthe seventh embodiment.

[0124]FIG. 55 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a third modification of theseventh embodiment.

[0125]FIG. 56 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a fourth modification ofthe seventh embodiment.

[0126]FIG. 57 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a fifth modification of theseventh embodiment.

[0127]FIG. 58 is a circuit diagram showing the connection of an MTJmemory cell according to an eighth embodiment of the present invention.

[0128]FIG. 59 is a structural diagram showing the MTJ memory cellarrangement according to the eighth embodiment.

[0129]FIG. 60 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to the eighth embodiment.

[0130]FIG. 61 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a first modification of theeighth embodiment.

[0131]FIG. 62 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a second modification ofthe eighth embodiment.

[0132]FIG. 63 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a third modification of theeighth embodiment.

[0133]FIG. 64 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a fourth modification ofthe eighth embodiment.

[0134]FIG. 65 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a fifth modification of theeighth embodiment.

[0135]FIG. 66 is a circuit diagram showing the connection of an MTJmemory cell according to a ninth embodiment of the present invention.

[0136]FIG. 67 is a timing chart illustrating the data write and readoperation to and from the MTJ memory cell according to the ninthembodiment.

[0137]FIG. 68 is a structural diagram showing the MTJ memory cellarrangement according to the ninth embodiment.

[0138]FIG. 69 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to the ninth embodiment.

[0139]FIG. 70 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a first modification of theninth embodiment.

[0140]FIG. 71 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a second modification ofthe ninth embodiment.

[0141]FIG. 72 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a third modification of theninth embodiment.

[0142]FIG. 73 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a fourth modification ofthe ninth embodiment.

[0143]FIG. 74 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a fifth modification of theninth embodiment.

[0144]FIG. 75 is a circuit diagram showing the connection of an MTJmemory cell according to a tenth embodiment of the present invention.

[0145]FIG. 76 is a structural diagram showing the MTJ memory cellarrangement according to the tenth embodiment.

[0146]FIG. 77 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to the tenth embodiment.

[0147]FIG. 78 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a first modification of thetenth embodiment.

[0148]FIG. 79 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a second modification ofthe tenth embodiment.

[0149]FIG. 80 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a third modification of thetenth embodiment.

[0150]FIG. 81 is a diagram illustrating the structure of memory array 10and its peripheral circuitry according to a fourth modification of thetenth embodiment.

[0151]FIG. 82 is a diagram illustrating the structure of a memory array10 and its peripheral circuitry according to a fifth modification of thetenth embodiment.

[0152]FIG. 83 is a schematic diagram showing the structure of a memorycell having a magnetic tunnel junction.

[0153]FIG. 84 is a conceptual diagram illustrating the data readoperation from the MTJ memory cell.

[0154]FIG. 85 is a conceptual diagram illustrating the data writeoperation to the MTJ memory cell.

[0155]FIG. 86 is a conceptual diagram illustrating the relation betweenthe direction of a data write current and the direction of a magneticfield in the data write operation.

[0156]FIG. 87 is a conceptual diagram showing the MTJ memory cellsarranged in rows and columns in an integrated manner.

[0157]FIG. 88 is a structural diagram of the MTJ memory cell provided ona semiconductor substrate.

[0158]FIG. 89 is a conceptual diagram illustrating the effects of themanufacturing variation on the data write margin.

[0159]FIG. 90 is a schematic diagram showing the structure of an MTJmemory cell using a diode.

[0160]FIG. 91 is a structural diagram of the MTJ memory cell of FIG. 90provided on a semiconductor substrate.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0161] Hereinafter, embodiments of the present invention will bedescribed in detail with reference to the accompanying drawings.

[0162] First Embodiment

[0163] Referring to FIG. 1, an MRAM device 1 according to the firstembodiment of the present invention conducts random access in responseto an external control signal CMD and address signal ADD, therebyconducting input of write data DIN and output of read data DOUT.

[0164] The MRAM device 1 includes a control circuit 5 for controllingthe overall operation of the MRAM device 1 in response to the controlsignal CMD, and a memory array 10 having a plurality of MTJ memory cellsarranged in n rows by m columns. Although the structure of the memoryarray 10 will be described later in detail, a plurality of write wordlines WWL and a plurality of read word lines RWL are providedcorresponding to the respective MTJ memory cell rows. Folded bit linepairs are provided corresponding to the respective MTJ memory cellcolumns. Each bit line pair is formed from bit lines BL and /BL. Notethat, hereinafter, a set of bit lines BL and /BL is also generallyreferred to as a bit line pair BLP.

[0165] The MRAM device 1 further includes a row decoder 20 forconducting row selection in the memory array 10 according to a rowaddress RA indicated by the address signal ADD, a column decoder 25 forconducting column selection in the memory array 10 according to a columnaddress CA indicated by the address signal ADD, a word line driver 30for selectively activating the read word line RWL and write word lineWWL based on the row selection result of the row decoder 20, a word linecurrent control circuit 40 for applying a data write current to thewrite word line WWL in the data write operation, and read/write controlcircuits 50, 60 for applying a data write current ±Iw and a sensecurrent Is in the data read and write operations.

[0166] Referring to FIG. 2, the memory array 10 includes the MTJ memorycells MC arranged in n rows by m columns (n, m: a natural number). TheMTJ memory cells MC have the structure shown in FIG. 83. The read wordlines RWL1 to RWLn and the write word lines WWL1 to WWLn are providedcorresponding to the respective MTJ memory cell rows (hereinafter, alsosimply referred to as “memory cell rows”). The bit lines BL1, /BL1 toBLm, /BLm forming the bit line pairs BLP1 to BLPm are providedcorresponding to the respective MTJ memory cell columns (hereinafter,also simply referred to as “memory cell columns”).

[0167] The MTJ memory cells MC in each row are coupled to either the bitlines BL or the bit lines /BL in an alternate manner. For example, forthe MTJ memory cells in the first memory cell column, the MTJ memorycell in the first row is coupled to the bit line /BL1, whereas the MTJmemory cell in the second row is coupled to the bit line BL1. Similarly,the MTJ memory cells in the odd rows are each connected to one bit line(/BL1 to /BLm) of a corresponding bit line pair, and the MTJ memorycells in the even rows are each connected to the other bit line (BL1 toBLm) of a corresponding bit line pair.

[0168] The memory array 10 further includes a plurality of dummy memorycells DMC respectively coupled to the bit lines BL1, /BL1 to BLm to/BLm. The dummy memory cells DMC are each coupled to either a dummy readword line DRWL1 or DRWL2, and are arranged in two rows by m columns. Thedummy memory cells coupled to the dummy read word line DRWL1 arerespectively coupled to the bit lines BL1, BL2, . . . BLm. The remainingdummy memory cells coupled to the dummy read word line DRWL2 arerespectively coupled to the bit lines /BL1, /BL2, . . . /BLm.

[0169] As described before, the resistance value of the MTJ memory cellMC varies according to the storage data level. Assuming that the MTJmemory cell MC storing H-level data has a resistance value Rh and thememory cell MC storing L-level data has a resistance value RI, aresistance value Rd of the dummy memory cell DMC is set to anintermediate value of RI and Rh. Note that RI<Rh in the embodiment ofthe present invention.

[0170] Hereinafter, the write word lines, read word lines, dummy readword lines, bit lines and bit line pairs are also generally denoted withWWL, RWL, DRWL, BL (/BL) and BLP, respectively. A specific write wordline, read word line, bit line, and bit line pair are denoted with, forexample, WWL1, RWL1, BL1 (/BL1) and BLP1, respectively.

[0171] The write word lines WWL1 to WWLn are coupled to the groundvoltage Vss by the word line current control circuit 40. Thus, a datawrite current Ip is applied to a write word line WWL activated to theselected state (high voltage state: power supply voltage Vcc) by theword line driver 30.

[0172] Hereinafter, the high voltage state (power supply voltage Vcc)and low voltage state (ground voltage Vss) of a signal line are alsosimply referred to as H level and L level, respectively.

[0173] Write column selection lines WCSL1 to WCSLm for conducting columnselection in the data write operation are provided corresponding to therespective memory cell columns. Similarly, read column selection linesRCSL1 to RCSLm for conducting column selection in the data readoperation are provided corresponding to the respective memory cellcolumns.

[0174] In the data write operation, the column decoder 25 activates oneof the write column selection lines WCSL1 to WCSLm to the selected state(H level) according to the decode result of the column address CA, i.e.,the column selection result. In the data read operation, the columndecoder 25 activates one of the read column selection lines RCSL1 toRCSLm to the selected state (H level) according to the column selectionresult.

[0175] Moreover, a write data bus pair WDBP for transmitting the writedata and a read data bus pair RDBP for transmitting the read data areprovided independently. The write data bus pair WDBP includes write databuses WDB and /WDB. Similarly, the read data bus pair RDBP includes readdata buses RDB and /RDB.

[0176] The read/write control circuit 50 includes a data write circuit51 a, a data read circuit 55 a, write column selection gates WCSG1 toWCSGm, read column selection gates RCSG1 to RCSGm and read gates RG1 toRGm. The write column selection gates WCSG1 to WCSGm, read columnselection gates RCSG1 to RCSGm and read gates RG1 to RGm are providedcorresponding to the respective memory cell columns.

[0177] One of the write column selection gates WCSG1 to WCSGm is turnedON according to the column selection result of the column decoder 25 soas to couple the write data buses WDB and /WDB of the write data buspair WDBP to the corresponding bit lines BL and /BL, respectively.

[0178] For example, the write column selection gate WCSG1 includes anN-type MOS transistor coupled between the write data bus WDB and the bitline BL1, and an N-type MOS transistor electrically coupled between thewrite data bus /WDB and the bit line /BL1. These MOS transistors areturned ON/OFF according to the voltage level on the write columnselection line WCSL1. More specifically, when the write column selectionline WCSL1 is activated to the selected state (H level), the writecolumn selection gate WCSG1 electrically couples the write data busesWDB and /WDB to the bit lines BL1 and /BL1, respectively. The writecolumn selection gates WCSG2 to WCSGm provided respectivelycorresponding to the other memory cell columns also have the samestructure as that described above.

[0179] The data write circuit 51 a operates in response to a controlsignal WE that is activated (to H level) in the data write operation anda control signal RE activated (to H level) in the data read operation.

[0180] Note that, hereinafter, the read column selection lines RCSL1 toRCSLm, write column selection lines WCSL1 to WCSLm, read columnselection gates RCSG1 to RCSGm, write column selection gates WCSG1 toWCSGm, and read gates RG1 to RGm are also generally denoted with RCSL,WCSL, RCSG, WCSG and RG, respectively.

[0181] Referring to FIG. 3, the data write circuit 51 a includes a datawrite current supply circuit 52 for supplying the data write current±Iw, and a pull-up circuit 53 for pulling up the bit line BL, /BL in thedata read operation.

[0182] The data write current supply circuit 52 includes a P-type MOStransistor 151 for supplying a constant current to an internal node Nw0,and a P-type MOS transistor 152 and current source 153 which form acurrent-mirror circuit for controlling a passing current through thetransistor 151.

[0183] The data write current supply circuit 52 further includesinverters 154, 155 and 156 operating in response to an operating currentsupplied from the internal node Nw0. The inverter 154 inverts thevoltage level of the write data DIN for transmission to an internal nodeNw1. The inverter 155 inverts the voltage level of the write data DINfor transmission to the input node of the inverter 156. The inverter 156inverts the output of the inverter 155 for transmission to an internalnode Nw2. Thus, the data write circuit 51 a sets the voltage on theinternal node Nw1 to one of the power supply voltage Vcc and groundvoltage Vss and the voltage on the internal node Nw2 to the other,according to the voltage level of the write data DIN.

[0184] The pull-up circuit 53 includes P-type MOS transistors 157 and158 electrically coupled between the power supply voltage Vcc and nudesNp1 and Np2, respectively. The transistors 157 and 158 receive aninverted signal /RE of the control signal RE at their gates.

[0185] The data write circuit 51 a further includes a switch SW1 a forselectively coupling one of the nodes Nw1 and Np1 to the write data busWDB, and a switch SWb for selectively coupling one of the nodes Nw2 andNp2 to the write data bus /WDB. The switches SW1 a and SW1 b operate inresponse to a control signal RWS.

[0186] In the data write operation, the switches SW1 a and SW1 b connectthe nodes Nw1 and Nw2 to the write data buses WDB and /WDB,respectively. As a result, in the data write operation, the voltage onthe write data bus WDB is set to one of the power supply voltage Vcc andground voltage Vss as well as the voltage on the write data bus /WDB tothe other, according to the write data level, in order to supply thedata write current ±Iw.

[0187] On the other hand, in the data read operation, the switches SW1 aand SW1 b couple the nodes Np1 and Np2 to the write data buses WDB and/WDB, respectively. As a result, in the data read operation, the writedata buses WDB and /WDB are pulled up to the power supply voltage Vcc bythe pull-up circuit 53.

[0188] Referring back to FIG. 2, since each of the read column selectiongate RCSG1 to RCSGm and each of the read gates RG1 to RGm, both providedcorresponding to the respective memory cell columns, have the samestructure, the respective structures of the read column selection gateRCSG1 and the read gate RG1 provided corresponding to the bit lines BL1,/BL1 are herein described exemplarily.

[0189] The read column selection gate RCSG1 and the read gate RG1 arecoupled in series between the read data bus RDB, /RDB and the groundvoltage Vss.

[0190] The read column selection gate RCSG1 includes an N-type MOStransistor coupled between the read data bus RDB and a node N1 a, and anN-type MOS transistor electrically coupled between the read data bus/RDB and a node Nib. These MOS transistors are turned ON/OFF accordingto the voltage on the read column selection line RCSL1. Morespecifically, when the read column selection line RCSL1 is activated tothe selected state (H level), the read column selection gate RCSG1electrically couples the read data buses RDB and /RDB to the nodes N1 aand N1 b, respectively.

[0191] The read gate RG1 includes N-type MOS transistors Q11 and Q12electrically coupled between the ground voltage Vss and the nodes N1 aand N1 b, respectively. The transistors Q1 and Q2 have their gatescoupled to the bit lines /BL1 and BL1, respectively. Accordingly, thevoltages on the nodes N1 a and N1 b change according to the voltages onthe bit lines /BL1 and BL1, respectively.

[0192] More specifically, when the voltage on the bit line BL1 is higherthan that on the bit line /BL1, the node N1 b are strongly pulled downtoward the ground voltage Vss by the transistor Q12. Therefore, thevoltage on the node N1 a becomes higher than that on the node N1 b. Onthe contrary, when the voltage on the bit line BL1 is lower than that onthe bit line /BL1, the voltage on the node N1 b becomes higher than thaton the node N1 a.

[0193] The voltage difference between the nodes N1 a and N1 b thusproduced is transmitted into the voltage difference between the readdata buses RDB and /RDB through the read column selection gate RCSG1.The data read circuit 55 a amplifies the voltage difference between theread data buses RDB and /RDB of the read data bus pair RDBP so as toproduce the read data DOUT.

[0194] Referring to FIG. 4, the data read circuit 55 a includes adifferential amplifier 56. In response to the voltages on the read databuses RDB and /RDB, the differential amplifier 56 amplifies the voltagedifference therebetween so as to produce the read data DOUT.

[0195] Referring back to FIG. 2, the read/write control circuit 60includes equalizing transistors 62-1 to 62-m that are turned ON/OFFaccording to a bit line equalizing signal BLEQ. The equalizingtransistors 62-1 to 62-m are provided corresponding to the respectivememory cell columns. For example, the equalizing transistor 62-1corresponds to the first memory cell, and electrically couples the bitlines BL1 and /BL1 to each other in response to activation (H level) ofthe bit line equalizing signal BLEQ.

[0196] Similarly, the equalizing transistors 62-2 to 62-m respectivelycorresponding to the other memory cell columns electrically couple thebit lines BL and /BL of the bit line pair BLP to each other in thecorresponding memory cell column, in response to activation of the bitline equalizing signal BLEQ.

[0197] The read/write control circuit 60 further includes prechargingtransistors 64-1 a, 64-1 b to 64-ma, 64-mb respectively provided betweenthe ground voltage Vss and the bit lines BL1, /BL1 to bit lines BLm,/BLm. The precharging transistors 64-1 a, 64-1 b to 64-ma, 64-mb areturned ON in response to activation of a bit line precharging signalBLPR so as to precharge the bit lines BL1, /BL1 to bit lines BLm, /BLmto the ground voltage Vss, respectively.

[0198] Note that, hereinafter, the equalizing transistors 62-1 to 62-mand precharging transistors 64-1 a, 64-1 b to 64-ma, 64-mb are alsogenerally referred to as equalizing transistors 62 and prechargingtransistors 64, respectively.

[0199] In the stand-by period of the MRAM device 1 as well as in theperiod other than the data read operation in the active period of theMRAM device 1, the bit line equalizing signal BLEQ produced by thecontrol circuit 5 is activated to H level in order to short-circuit thebit lines BL and /BL of each folded bit line pair BL.

[0200] On the other hand, in the data read operation in the activeperiod of the MRAM device 1, the bit line equalizing signal BLEQ isinactivated to L level. In response to this, the bit lines BL and /BL ofeach bit line pair BL in each memory cell column are electricallydisconnected from each other.

[0201] The bit line precharging signal BLPR is also produced by thecontrol circuit 5. In the active period of the MRAM device 1, the bitline precharging signal BLPR is activated to H level at least during aprescribed period before the data read operation. During the data readoperation in the active period of the MRAM device 1, the bit lineprecharging signal BLPR is inactivated to L level, so that theprecharging transistors 64 are turned OFF.

[0202] Hereinafter, the data read and write operations of the MRAMdevice according to the first embodiment will be described withreference to FIG. 5.

[0203] First, the data write operation will be described.

[0204] Referring to FIG. 5, the write column selection line WCSLcorresponding to the column selection result is activated to theselected state (H level), so that the corresponding write columnselection gate WCSG is turned ON. In response to this, the bit lines BLand /BL corresponding to the column selection result are respectivelycoupled to the write data buses WDB and /WDB.

[0205] Moreover, in the data write operation, the equalizing transistor62 is turned ON to short-circuit the bit lines BL and /BL.

[0206] As described before, the data write circuit 51 a sets the voltageon the write data bus WDB to one of the power supply voltage Vcc andground voltage Vss, and the voltage on the write data bus /WDB to theother. For example, in the case where the write data DIN is L-leveldata, the voltages on the nodes Nw2 and Nw1 shown in FIG. 3 arerespectively set to the power supply voltage Vcc and the ground voltageVcc. Therefore, the data write current -Iw for writing the L level datais applied to the write data bus WDB. The data write current -Iw issupplied to the bit line BL through the write column selection gateWCSG.

[0207] The data write current −Iw flowing through the bit line BL turnsaround at the equalizing transistor 62. Thus, the data write current +Iwof the opposite direction flows through the other bit line /BL. The datawrite current +Iw flowing through the bit line /BL is transmitted to thewrite data bus /WDB through the write column selection gate WCSG.

[0208] Moreover, one of the write word lines WWL is activated to theselected state (H level) according to the row selection result, and thedata write current Ip is applied thereto. Accordingly, in the memorycell column corresponding to the column selection result, the data iswritten to the MTJ memory cell corresponding to the selected write wordline WWL. At this time, the L-level data is written to the memory cellMC coupled to the bit line BL, whereas the H level data is written tothe memory cell MC coupled to the bit line /BL.

[0209] In the case where the write data DIN is H-level data, thevoltages on the nodes Nw1 and Nw2 are set in the opposite manner to thatdescribed above. Therefore, the data write current flows through the bitlines BL and /BL in the opposite direction to that described above forthe data write operation. Thus, the data write current ±Iw having thedirection corresponding to the level of the write data DIN is suppliedto the bit lines BL and /BL.

[0210] In the data write operation, the read word lines RWL are retainedin the non-selected state (L level).

[0211] For example, by activating the bit line precharging signal BLPR(to H level) in the data write operation, the voltages on the bit linesBL and /BL in the data write operation are set to the ground voltage Vsscorresponding to the precharge voltage level for the data readoperation.

[0212] Similarly, the read data buses RDB and /RDB are set to the powersupply voltage Vcc corresponding to the precharge voltage for the dataread operation. Thus, the voltages on the bit lines BL, /BL and the readdata buses RDB, /RDB corresponding to the non-selected columns in thedata write operation correspond to the precharge voltage for the dataread operation. This eliminates the need to conduct an additionalprecharging operation before the data read operation, increasing thespeed of the data read operation.

[0213] Hereinafter, the data read operation will be described.

[0214] Before the data read operation, the read data buses RDB, /RDB andthe bit lines BL, /BL are precharged to the power supply voltage Vcc andthe ground voltage Vss, respectively.

[0215] In the data read operation, the write data buses WDB and /WDB arepulled up to the power supply voltage Vcc by the pull-up circuit 53.Moreover, according to the column selection result, both a correspondingread column selection line RCSL and a corresponding write columnselection line WCSL are activated to the selected state (H level).

[0216] Thus, the write data buses WDB and /WDB are electrically coupledto the bit lines BL and /BL of the selected column through the writecolumn selection gate WCSG, respectively. Accordingly, in the data readoperation, the bit lines BL and /BL corresponding to the selected memorycell column are pulled up to the power supply voltage Vcc.

[0217] One of the read word lines RWL is activated to the selected state(H level) according to the row selection result, whereby thecorresponding memory cell MC is coupled to one of the bit lines BL and/PL.

[0218] Moreover, one of the dummy read word lines DRWL1 and DRWL2 isactivated, whereby the other of the bit lines BL and /BL, which is notcoupled to the MTJ memory cell MC, is coupled to the dummy memory cellDMC.

[0219] In the case where an odd row is selected according to the rowselection result and the bit line /BL is coupled to the MTJ memory cellMC, the dummy read word line DRWL1 is activated, so that the bit line BLis coupled to the dummy memory cell DMC. On the contrary, in the casewhere an even row is selected according to the row selection result andthe bit line BL is coupled to the MTJ memory cell MC, the dummy readword line DRWL2 is activated, so that the bit line /BL is coupled to thedummy memory cell DMC.

[0220] In the selected MTJ memory cell MC, the access transistor ATR isturned ON, whereby the sense current Is flows through a path of thepulled-up bit line BL or /BL, memory cell MC and ground voltage Vss.Accordingly, a voltage change ΔV1 corresponding to the stored data levelis produced on one of the bit lines BL and /BL, which is coupled to theMTJ memory cell. FIG. 5 exemplarily shows a voltage change for the casewhere the MTJ memory cell MC to be read retains H-level data, that is,the MTJ memory cell MC to be read has a resistance value Rh.

[0221] As described above, the resistance value Rd of the dummy memorycell DMC is set to an intermediate value of the resistance values Rh andRl of the MTJ memory cell MC. Accordingly, a voltage change ΔVmcorresponding to the intermediate resistance value Rd is produced on theother of the bit lines BL and /BL, which is coupled to the dummy memorycell DMC.

[0222] Accordingly, the relative relation between the voltages on thebit lines BL and /BL of the bit line pair BLP corresponding to theselected memory cell column changes according to the read storage datalevel. With such a voltage difference between the bit lines BL and /BL,the read data buses RDB and /RDB are driven through the read gate.

[0223] More specifically, when the voltage on the bit line BL is higherthan that on the bit line /BL, the read data bus /RDB is more stronglydriven toward the ground voltage Vss through the read gate RG than isthe read data bus RDB (the voltage change ΔVb1>ΔVbm in FIG. 5). Thevoltage difference between the read data buses RDB and /RDB thusproduced is amplified by the data read circuit 55 a, so that the H-levelread data DOUT can be output.

[0224] On the contrary, in the case where the MTJ memory cell MC to beread retains L-level data, that is, in the case where the voltage on thebit line /BL is higher than that on the bit line BL, the read data busRDB is more strongly driven toward the ground voltage Vss through theread gate RG than is the read data bus /RDB. The voltage differencebetween the read data buses RDB and /RDB thus produced is amplified bythe data read circuit 52, so that the L-level read data DOUT can beoutput.

[0225] Thus, driving the read data buses RDB and /RDB through the readgate RG enables the data read operation to be conducted without applyingthe sense current to the read data buses RDB and /RDB. This reduces theRC load on the sense current path, whereby a voltage change required toread the data can be quickly produced on the bit lines BL and /BL. Thus,the data can be read at a high speed, whereby the access speed to theMRAM device can be increased.

[0226] Moreover, the pulled-up write data buses WDB and /WDB arerespectively coupled to the bit lines BL and /BL through the writecolumn selection gate WDSG so as to supply the sense current Is.Therefore, the sense current Is can be applied only to the bit lines BLand /BL corresponding to the memory cell column to be read. This canavoid unnecessary current consumption in the data read operation.

[0227] Moreover, the folded bit line pair causes the data write currentto turn around at the equalizing transistor. Therefore, the data writecurrent of the different directions can be supplied merely bycontrolling one end of the bit line BL to one of the power supplyvoltage Vcc and ground voltage Vss and one end of the bit line /BL tothe other. Thus, a voltage of different polarity (negative voltage) isnot necessary, and the direction of the current can be switched merelyby setting the voltage on the write data bus WDB to one of the powersupply voltage and ground voltage and the voltage on the write data bus/WDB to the other. Accordingly, the structure of the data write circuit51 a can be simplified. Moreover, the structure for sinking the datawrite current ±Iw (i.e., a current path to the ground voltage Vss) neednot be provided in the read/write control circuit 60, and the data writecurrent ±Iw can be controlled only with the equalizing transistor 62. Asa result, the circuit structure associated with the data write current±Iw within the read/write control circuits 50 and 60 can be reduced insize.

[0228] Moreover, since the data read operation is conducted using thedummy memory cells in the structure having the folded bit line pairs, asufficient data read margin can be ensured.

[0229] First Modification of First Embodiment

[0230] Referring to FIG. 6, the structure according to the firstmodification of the first embodiment is different from that of the firstembodiment in that the precharging transistors 64-1 a, 64-1 b to 64-m 1to 64-mb are provided in order to precharge the bit lines BL1, /BL1 toBLm, /BLm to the power supply voltage Vcc. Moreover, the data writecircuit 51 a and the data read circuit 55 a are replaced with a datawrite circuit 51 b and data read circuit 55 b, respectively. Since thestructure is otherwise the same as that of the first embodiment shown inFIG. 2, detailed description thereof will not be repeated.

[0231] Referring to FIG. 7, the data write circuit 51 b includes thedata write current supply circuit 52 shown in FIG. 3. The data writecircuit 51 b couples the output nodes Nw1 and Nw2 of the data writecurrent supply circuit 52 directly to the write data bus pair WDB and/WDB, respectively. The data write circuit 51 b does not include thepull-up circuit 53 and the switches SW1 a, SW1 b, and does not conductthe pull-up operation in the data read operation.

[0232] Referring to FIG. 8, the data read circuit 55 b includes transfergates TGa and TGb respectively provided between the read data buses RDB,/RDB and the input nodes of the differential amplifier 56. The transfergates TGa and TGb couple the read data buses RDB and /RDB to therespective input nodes of the differential amplifier 53 according to atrigger pulse φr.

[0233] The data read circuit 55 b further includes a latch circuit 57for latching the output of the differential amplifier 56, and a transfergate TGc provided between the differential amplifier 56 and the latchcircuit 57. Like the transfer gates TGa and TGb, the transfer gate TGcoperates in response to the trigger pulse φr. The latch circuit 57outputs the read data DOUT.

[0234] Accordingly, at the timing the trigger pulse φr is activated to Hlevel, the data read circuit 55 b amplifies the voltage differencebetween the read data buses RDB and /RDB so as to set the level of theread data DOUT. During the inactive (L level) period of the triggerpulse φr, the level of the read data DOUT is retained in the latchcircuit 57.

[0235] Hereinafter, the data read and write operations of the MRAMdevice according to the first modification of the first embodiment willbe described with reference to FIG. 9.

[0236] Referring to FIG. 9, the precharge voltage of the bit lines BLand /BL before the data write operation is set to the power supplyvoltage Vcc. In the data write operation, the trigger pulse φr isretained in the inactive state (L level). Since the data write operationis otherwise the same as that shown by the timing chart of FIG. 5,detailed description thereof will not be repeated.

[0237] Hereinafter, the data read operation will be described. Beforethe data read operation, the bit lines BL, /BL and the read data busesRDB, /RDB are precharged to the power supply voltage Vcc. On the otherhand, the write column selection lines WCSL are retained in the inactivestate (L level) in the data read operation. In other words, unlike thefirst embodiment, the bit lines BL and /BL are not pulled up to thepower supply voltage Vcc in the data read operation.

[0238] With the bit lines BL and /BL precharged to the power supplyvoltage Vcc, the read word line RWL is selectively activated accordingto the row selection result. In response to this, the access transistorATR is turned ON in the MTJ memory cell to be read, whereby the path ofthe sense current Is is formed. Thus, the voltage on the bit line BL,/BL starts reducing.

[0239] The voltage reducing rate of the bit line BL, /BL is determinedbased on the resistance value of the memory cell MC or dummy memory cellDMC coupled to the bit line BL, /BL. More specifically, the bit line BL,/BL coupled to the memory cell MC storing L-level data has a highvoltage reducing rate, whereas the bit line BL, /BL coupled to thememory cell MC storing H-level data has a low voltage reducing rate. Thebit line BL, /BL coupled to the dummy memory cell DMC has anintermediate voltage reducing rate.

[0240]FIG. 9 exemplarily shows the waveform of the bit line for the casewhere the MTJ memory cell MC to be read retains L-level data. FIG. 9also shows the waveform of the bit line coupled to the dummy memory cellDMC.

[0241] As in the first embodiment, the voltage reduction on the bit lineBL, /BL is transmitted to the read data bus RDB, /RDB through the readgate RG. Accordingly, the trigger pulse φr is activated at a prescribedtiming during reduction in voltage on the read data bus RDB, /RDB,whereby the voltage difference between the read data buses RDB and /RDBis taken in the latch circuit 57. Thus, the data read operation can beconducted at a high speed as in the first embodiment.

[0242] Note that the structure according to the first modification ofthe first embodiment eliminates the need to supply the sense current Isin the data read operation, allowing for further reduction in powerconsumption.

[0243] Second Modification of First Embodiment

[0244] In the second modification of the first embodiment, the data readoperation through the read gate RG as described in the first embodimentand the first modification thereof is applied to the open bit linestructure.

[0245] Referring to FIG. 10, in the structure according to the secondmodification of the first embodiment, open bit lines BL1 to BLm areprovided corresponding to the respective memory cell columns. The writecolumn selection gates WCSG1 to WCSGm are provided between the writedata bus WDB and the bit lines BL1 to BLm, respectively. The writecolumn selection gates WCSG1 to WCSGm are turned ON/OFF according to thevoltage on the respective write column selection lines WCSL1 to WCSLm.

[0246] The read/write control circuit 60 includes bit line currentcontrol transistors 63-1 to 63-m provided between the write data bus/WDB and the bit lines BL1 to BLm, respectively. Like the write columnselection gates WCSG1 to WCSGm, the bit line current control transistors63-1 to 63-m are turned ON/OFF according to the voltage on therespective write column selection lines WCSL1 to WCSLm.

[0247] The precharging transistors 64-1 to 64-m precharge the respectivebit lines BL1 to BLm to the power supply voltage Vcc in response to thebit line precharging signal BLPR.

[0248] As in the case of FIG. 6, the data write circuit 51 b suppliesthe data write current ±Iw to the write data buses WDB and /WDB. Withsuch a structure, the data write current can be supplied to the selectedmemory cell column as in the case of the first modification of the firstembodiment.

[0249] In each memory cell column, the read column selection gate RCSGand the read gate RG are coupled in series between the read data bus RDBand the ground voltage Vss. For example, in the first memory cellcolumn, the read column selection gate RCSG1 and the read gate RG1 arecoupled in series between the read data bus RDB and the ground voltageVss. The read column selection gate RCSG1 is formed from an N-type MOStransistor that is turned ON/OFF according to the read column selectionline RCSL1, and the read gate RG1 is formed from an N-type MOStransistor having its gate coupled to the bit line BL1.

[0250] With such a structure, the read data bus RDB can be drivenaccording to the voltage on the corresponding bit line BL through theread gate RG in the selected memory cell column. Accordingly, when theread word line RWL is activated with the bit lines BL1 to BLm prechargedto the power supply voltage Vcc, a sense current path of the bit line BL(precharged to the power supply voltage Vcc), MTJ memory cell and groundvoltage Vss can be formed in the selected memory cell.

[0251] Thus, the voltage on the corresponding bit line BL reduces at arate corresponding to the storage data level in the selected MTJ memorycell MC. Accordingly, as in the first modification of the firstembodiment, the voltage level on the bit line is taken in the data readcircuit 55 c at an appropriate timing during reduction in voltage on theread data bus RDB, and this voltage is compared with a reference voltageVm determined based on the voltage reduction rate of the dummy memorycell DMC in the first modification of the first embodiment. As a result,the read data DOUT can be output. In other words, the structure of thedata read circuit 55 c can be implemented with the data read circuit 55c of FIG. 8 arranged such that one of the input nodes of thedifferential amplifier 56 receives the reference voltage Vm instead ofthe voltage on the read data bus /RDB.

[0252] Note that it is also possible to conduct the same data readoperation as that in the first embodiment with the bit lines BL pulledup to the power supply voltage Vcc. In such a case, turning ON/OFF ofthe write column selection gate WCSG and bit line current controltransistor 62 is controlled in the same manner as that in the firstembodiment, and the data write circuit 51 b is replaced with the datawrite circuit 51 a including the pull-up circuit 53.

[0253] In this case, the write column selection gate WCSG is turned ONboth in the data read and write operations according to the columnselection result, but the bit line current control transistor 62 can beturned ON only in the data write operation.

[0254] Moreover, although the specific structure is not shown in thefigure, the data read circuit 55 c can be replaced with a differentialamplifier for producing the read data DOUT according to the comparisonresult between the voltage on the write data bus WDB and the referencevoltage that is set corresponding to the resistance value Rd of thedummy memory cell DMC.

[0255] Thus, the same data read and write operations as those of thefirst embodiment and the first modification thereof can be conductedeven in the open bit line structure.

[0256] Third Modification of First Embodiment

[0257] In the third modification of the first embodiment, the number ofgate circuits associated with column selection is reduced.

[0258] Referring to FIG. 11, the structure according to the thirdmodification of the first embodiment includes a data input/output (I/O)line pair DI/OP formed from data I/O lines IO and /IO.

[0259] Column selection gates CSG1 to CSGm are provided between the dataI/O line pair DI/OP and the bit line pairs BLP1 to BLPm, respectively.According to the column selection result, the column selection gate CSG1to CSGm is turned ON/OFF according to the voltage on a correspondingcolumn selection line CSL1 to CSLm that is selectively activated to Hlevel by the column decoder 25. More specifically, both in the data readand write operations, the column selection gate CSG1 to CSGm is turnedON/OFF according to the column selection result.

[0260] Note that the column selection gates CSG1 to CSGm are alsogenerally denoted with CSG.

[0261] A read gate for increasing the data read speed is provided as acommon read gate RCG coupled between the read data bus pair RDBP and thedata I/O line pair DI/OP. A write selection gate WCG is further providedbetween the data I/O line pair DI/OP and the write data bus pair WDBP.

[0262] Since the respective structures of the memory array 10 and theread/write control circuit 60 are the same as those of FIG. 2, detaileddescription thereof will not be repeated. Moreover, the respectivestructures and operations of the data write circuit 51 a and the dataread circuit 55 a are also the same as those described above. Therefore,detailed description thereof will not be repeated.

[0263] The read gate RCG includes N-type MOS transistors Qc1 and Qc3coupled in series between the read data bus RDB and the ground voltageVss, and N-type MOS transistors Qc2 and Qc4 coupled in series betweenthe read data bus /RDB and the ground voltage Vss. The transistors Qc1and Qc2 receive the control signal RE at their gates. The transistorsQc3 and Qc4 are connected at their gates to the data I/O lines /IO andIO, respectively.

[0264] Thus, in the data read operation in which the control signal REis activated to H level, the read data buses RDB, /RDB can be driven bythe bit lines BL, /BL corresponding to the selected memory cell columnthrough the column selection gate CSG and the data I/O line pair DI/OP.

[0265] Accordingly, the memory cell columns in the memory array 10sharing the data I/O line pair DI/OP share the common read gate RCG,achieving reduction in circuit area. With the common read gate RCG aswell, the data read operation can be conducted at a high speed withoutsupplying the sense current Is to the read data buses RDB, /RDB.

[0266] The write selection gate WCG includes an N-type MOS transistorQc5 electrically coupled between the write data bus WDB and the data I/Oline IO, and an N-type MOS transistor Qc6 electrically coupled betweenthe write data bus /WDB and the data I/O line /IO. The transistors Qc5and Qc6 receive a control signal SG at their gates. The control signalSG is activated in the data write operation according to the controlsignal WE. In the data read operation as well, the control signal SG maybe activated according to the control signal RE. Thus, the transistorsQc5 and Qc6 are turned ON, and the pull-up circuit 53 within the datawrite circuit 51 a pulls up the bit lines BL and /BL corresponding tothe selected memory cell column, whereby the sense current Is can besupplied.

[0267] In the data write operation, the transistors Qc1 and Qc2 in thecommon read gate RCG are turned OFF. Therefore, the voltages on the readdata buses RDB and /RDB do not relate to the data I/O lines IO and /10.

[0268] On the other hand, in response to activation (H level) of thecontrol signal SG, the transistors Qc5 and Qc6 in the write selectiongate WCG electrically couple the write data buses WDB and /WDB to thedata I/O lines IO and /IO, respectively. Thus, the data write current+Iw can be supplied to the bit lines BL and /BL corresponding to theselected memory cell column.

[0269] As in the case of FIG. 6, the data write circuit 51 a and thedata read circuit 55 a may be replaced with the data write circuit 51 band the data read circuit 55 b, and the power supply voltage Vcc may beused as the precharge voltage of the bit lines BL1, /BL1 to BLm, /BLm.Thus, the data read operation according to the voltage reduction rate onthe bit line can be conducted as in the first modification of the firstembodiment.

[0270] In this case, the control signal SG must be inactivated to Llevel in the data read operation in order to turn OFF the writeselection gate WCG. For example, instead of the control signal SG, thecontrol signal WE can be directly input to the gates of the transistorsQc5 and Qc6.

[0271] Second Embodiment

[0272] In the second embodiment is described the structure for adjustinga data write current in order to ensure a data write margincorresponding to variation in magnetic characteristics of the memorycells due to manufacturing variation.

[0273] Referring to FIG. 12, a data write circuit according to thesecond embodiment is different from the data write circuit 51 a shown inFIG. 3 in that the data write current of the second embodiment furtherincludes a data write current adjustment circuit 200.

[0274] The data write current adjustment circuit 200 outputs a referencevoltage Vrw for controlling the current amount of the current source 153in the data write current supply circuit 52. The data write currentsupply circuit 52 includes an N-channel MOS transistor receiving thereference voltage Vrw at its gate. This N-channel MOS transistorcorresponds to the current source 153. Accordingly, the current amountsupplied to the node Nw0 through the transistor 151 forming a currentmirror with the transistor 152 in the data write current supply circuit52, i.e., the amount of the data write current ±Iw, can be adjustedaccording to the reference voltage Vrw.

[0275] The data write current adjustment circuit 200 includes areference voltage external input terminal 202 for receiving an externalreference voltage Vre1, a test input terminal 204 for receiving a testmode entry signal TE for switching generation of the reference voltageVrw between the test mode and the normal mode, and an internal referencevoltage generation circuit 206 for generating an internal referencevoltage Vri1.

[0276] The data write current adjustment circuit 200 further includes atransfer gate TGf1 coupled between the reference voltage external inputterminal 202 and a node Nf1, and a transfer gate TGf2 provided betweenthe internal reference voltage generation circuit 206 and the node Nf1.The transfer gates TGf1 and TGf2 are turned ON in a complementary mannerin response to the test mode entry signal TE. The node Nf1 is coupled tothe gate of the N-channel MOS transistor corresponding to the currentsource 153.

[0277] With such a structure, in the normal operation in which the testmode entry signal TE is inactivated to L level, the transfer gates TGf2and TGf1 are turned ON and OFF, respectively. Accordingly, the referencevoltage Vri1 produced by the internal reference voltage generationcircuit 206 is input as the reference voltage Vrw to the gate of thetransistor corresponding to the current source 153.

[0278] On the other hand, in the test operation in which the test modeentry signal TE is activated to H level, the transfer gates TGf1 andTGf2 are turned ON and OFF, respectively. Accordingly, the externalreference voltage Vre1 applied to the reference voltage external inputterminal 202 is input to the gate of the transistor corresponding to thecurrent source 153.

[0279] Accordingly, in the test mode, the external reference voltageVre1 at an arbitrary level is input in response to activation of thetest mode entry signal TE, so that the data write margin can be tested.Thus, the manufacturing variation in magnetic characteristics of the MTJmemory cells can be compensated for, whereby the adjustment testing ofthe data write current amount for appropriately ensuring a data writemargin can be conducted. For example, this adjustment testing can beconducted such that the data write current +Iw is gradually reduced fromthe standard value, whereby whether or not a desired data write marginis ensured for every MTJ memory cell is confirmed.

[0280] The level of the voltage Vri1 produced by the internal referencevoltage generation circuit 206 need only be set to a proper value of thereference voltage Vrw that is found from such adjustment testing.

[0281] Thus, variation in magnetic characteristics of the MTJ memorycells due to the manufacturing variation can be compensated for,allowing the data write operation in the normal operation to beconducted based on a proper data write current amount.

[0282] Referring to FIG. 13, a word line driver according to the secondembodiment includes write word drivers WWD1 to WWDn providedcorresponding to the write word lines WWL1 to WWLn, respectively. Eachof the write word drivers WWD1 to WWDn is formed from, e.g., aninverter. Note that, hereinafter, the write word drivers WWD1 to WWDnare also generally denoted with WWD.

[0283] The row decoder 20 activates one of row decode signals RD1 toRDn, i.e., the row decode signal corresponding to the selected row, to Llevel according to the row address RA. The row decode signals RD1 to RDnare transmitted to the word line driver 30. The write word drivers WWD1to WWDn of the word line driver 30 receive the row decode signals RD1 toRDn, respectively. When a row decode signal is inactivated to L level,the corresponding write word driver WWD activate the corresponding writeword line WWL to the selected state (H level).

[0284] In the data write operation, the write word driver WWD1 to WWDnsupplies the data write current Ip to the write word line WWLcorresponding to the selected row.

[0285] The word line driver 30 further includes a data write currentsupply circuit 32 for supplying the data write current Ip to the worddrivers WWD 1 to WWDn, and a data write current adjustment circuit 210for adjusting the amount of the data write current Ip.

[0286] The data write current supply circuit 32 includes P-channel MOStransistors 33 a and 33 b electrically coupled between the power supplyvoltage Vcc and nodes Np0 and Np1, and an N-channel MOS transistor 34electrically coupled between the node Np1 and the ground voltage Vss.The data write current Ip to be supplied to each write word driver WWDis transmitted to the node Np0.

[0287] The node Np1 is electrically coupled to the gates of thetransistors 33 a and 33 b. The transistor 34 receives at its gate areference voltage Vrp output from the data write current adjustmentcircuit 210. Thus, the transistor 34 operates as a current source forsupplying the current amount according to the reference voltage Vrp.Since the transistors 33 a, 33 b and 34 form a current mirror circuit,the current amount supplied through the data write current supplycircuit 32 to the node Np0, i.e., the amount of the data write currentIp, can be adjusted according to the reference voltage Vrp output fromthe data write current adjustment circuit 210.

[0288] The data write current adjustment circuit 210 has the samestructure as that of the data write current adjustment circuit 200described in connection with FIG. 11.

[0289] More specifically, the data write current adjustment circuit 210includes a reference voltage external input terminal 212 for receivingan external reference voltage Vre2, a test input terminal 214 forreceiving a test mode entry signal TE, and an internal reference voltagegeneration circuit 216 for generating an internal reference voltageVri2.

[0290] The data write current adjustment circuit 210 further includes atransfer gate TGf3 coupled between the reference voltage external inputterminal 212 and a node Nf2, and a transfer gate TGf4 provided betweenthe internal reference voltage generation circuit 216 and the node Nf2.The transfer gates TGf3 and TGf4 are turned ON in a complementary mannerin response to the test mode entry signal TE. The node Nf2 is coupled tothe gate of the transistor 34 operating as a current source.

[0291] Accordingly, in each of the normal operation and the test modeoperation, the reference voltage Vri2 produced by the internal referencevoltage generation circuit 216 and the external reference voltage Vre2applied to the reference voltage external input terminal 212 are inputto the gate of the transistor 34 according to the test mode entry signalTE.

[0292] As a result, in the test mode, the external reference voltageVre2 at an arbitrary level is input, so that the data write margin canbe tested. Thus, the manufacturing variation in magnetic characteristicsof the MTJ memory cells can be compensated for, whereby the adjustmenttesting of the data write current amount for appropriately ensuring adata write margin can be facilitated. For example, this adjustmenttesting can be conducted such that the data write current Ip isgradually reduced from the standard value, whereby whether or not adesired data write margin is ensured for every MTJ memory cell isconfirmed.

[0293] The level of the voltage Vri2 produced by the internal referencevoltage generation circuit 216 need only be set to a proper value of thereference voltage Vrw that is found from such adjustment testing.

[0294] Thus, variation in magnetic characteristics of the MTJ memorycells due to the manufacturing variation can be compensated for,allowing the data write operation in the normal operation to beconducted based on a proper data write current amount.

[0295] Modification of Second Embodiment

[0296] Referring to FIG. 14, a data write current adjustment circuit 230according to the modification of the second embodiment outputs areference voltage Vref for adjusting the amount of the data writecurrent. Note that the data write current adjustment circuit 230 shownin FIG. 13 may be replaced either with the data write current adjustmentcircuit 200 for adjusting the data write current +Iw to be supplied tothe bit line or with the data write current adjustment circuit 21 foradjusting the data write current Ip to be supplied to the write wordline.

[0297] Referring to FIG. 14, the data write current adjustment circuit230 includes a tuning input portion 231 a and a voltage adjustmentportion 231 b for adjusting the reference voltage Vref according to thesetting of the tuning input portion 231 a.

[0298] The voltage adjustment portion 231 b includes a P-channel MOStransistor 232 electrically coupled between a node Nt1 producing thereference voltage Vref and the power supply voltage Vcc, and anoperational amplifier 234 for amplifying the voltage difference betweenthe voltage on a node Nt2 and a prescribed voltage Vref0 for output tothe gate of the transistor 232.

[0299] The voltage adjustment portion 231 b further includes a P-channelMOS transistor 240 electrically coupled between the nodes Nt1 and Nt2,and P-channel MOS transistors 241, 242, 243 and 244 coupled in seriesbetween the node Nt2 and the ground voltage Vss. The transistors 240 to244 have their gates coupled to the ground voltage Vss. Thus, thetransistors 240 to 244 serve as resistive elements.

[0300] With the gate voltage of the transistor 232 being controlled bythe operational amplifier 234, the level of the reference voltage Vrefis controlled so that the voltage on the node Nt2 becomes equal to theprescribed voltage Vref0. The prescribed voltage Vref0 is set in view ofthe reference voltage Vref.

[0301] Herein, the voltage Vα on the node Nt2 is obtained from thereference voltage Vref divided by the transistors 240 to 244 serving asresistive elements. Provided that this voltage division ratio is definedas α (α=Vref/Vα), the reference voltage Vref is given by the followingexpression using the prescribed voltage Vref0 input to the operationalamplifier 234: Vref=α·Vref0.

[0302] The voltage division ratio α is determined from the ratio of theresistance value between the node Nt1 and the ground voltage Vss to theresistance value between the node Nt2 and the ground voltage Vss, whichare set according to the input to the tuning input portion 231 a.

[0303] Thus, the reference voltage Vref is not directly programmed, butthe voltage division ratio α for the input voltage to the operationalamplifier 234 is programmed, whereby the response property and noiseresistance of the reference voltage Vref can be improved.

[0304] The tuning input portion 231 a includes sets of a fuse elementserving as a program element and a transfer gate. These sets areprovided in parallel with the transistors 241 to 243, respectively. Forexample, a transfer gate TGt1 and a fuse element 251, which areconnected in series with each other, are provided in parallel with thetransistor 241. A transfer gate TGt2 and a fuse element 252, which areconnected in series with each other, are provided in parallel with thetransistor 242. Similarly, a transfer gate TGt3 and a fuse element 253,which are connected in series with each other, are provided in parallelwith the transistor 243.

[0305] The fuses can be blown by radiating the laser light from theoutside directly to the fuse elements 251 to 253, or by applying a highvoltage signal from the outside through respective blow input nodes 281to 283.

[0306] The tuning input portion 231 a further includes an input terminal270 for receiving a control signal TT that is activated upon conductingthe tuning testing of the data write current, input terminals 271 to 273for receiving tuning test signals TV1 to TV3, respectively, a logic gate261 for controlling turning ON/OFF of the transfer gate TGt1 accordingto the respective levels of the control signal TT and tuning test signalTV1, a logic gate 262 for controlling turning ON/OFF of the transfergate TGt2 according to the respective levels of the control signal TTand tuning test signal TV2, and a logic gate 263 for controlling turningON/OFF of the transfer gate TGt3 according to the respective levels ofthe control signal TT and tuning test signal TV3.

[0307] In the normal operation, the control signal TT is inactivated toL level. Therefore, the respective output signals of the logic gates 261to 263 are set to H level. In response to this, the transfer gates TGt1to TGt3 are all turned ON. Thus, the voltage division ratio α isdetermined whether the fuse elements 251 to 253 have been blown or not.

[0308] In the tuning input portion 231 a, the fuse-blown state can besimulated by setting the output signal of the logic gate 261 to 263 to Llevel by the input signal to the input terminal 270 to 273 so as to turnOFF the corresponding transfer gate TGt1, TGt2, TGt3., For example, inthe case where the tuning test is conducted with the control signal TTactivated (to H level), the transfer gate TGt1 can be turned OFF byactivating the tuning test signal TV1 to H level. Thus, the stateequivalent to that in which the fuse element 251 has been blown can beobtained.

[0309] Similarly, the fuse-blown state can also be simulated for thefuse elements 252 and 253.

[0310] Accordingly, the voltage division ratio α is changed with thecontrol signal TT and the tuning test signals TV1 to TV3 that are inputto the respective input terminals 270 to 273, so that the referencevoltage Vref for adjusting the data write current can be set in avariable manner.

[0311] Therefore, in the tuning test, the voltage division ratio α isadjusted reversibly without actually blowing any fuse, whereby theadjustment test of the data write current amount for appropriatelyensuring the data write margin can be facilitated.

[0312] After the tuning test is completed, the fuse element is actuallyblown according to the test result. Thus, the reference voltage Vref forobtaining an appropriate data write current can be programmed to thetuning input portion 231 a in a non-volatile manner. As a result, thedata write current adjustment circuit 230 produces a programmed,appropriate reference voltage Vref in the normal operation. Therefore,the manufacturing variation in magnetic characteristics of the MTJmemory cells is compensated for, and the data write operation in thenormal operation can be conducted.

[0313] Note that FIG. 14 shows the structure including the referencevoltage external input terminals 202 (212) and 204 (214) for receivingthe external reference voltage, as well as the transfer gates TGf1(TGf3) and TGf2 (TGf4). However, these elements may be omitted so thatthe reference voltage Vref is directly applied to the gate of thetransistor 153 (34). In this case as well, the tuning test of the datawrite current can be conducted.

[0314] Such a structure enables the tuning test to be conducted merelyby inputting a digital signal. That is, the tuning testing can beconducted more efficiently as compared to the respective structures ofthe data write current adjustment circuits 200 and 210 shown in FIGS. 12and 13. Moreover, this structure eliminates the need to conduct theadjustment corresponding to the output voltage adjustment of theinternal reference voltage generation circuits 206 and 216 included inthe data write current adjustment circuits 200 and 210, thereby reducingthe load for adjustment.

[0315] Note that the number of transistors for setting the voltagedivision ratio α is not limited to that in the example shown in FIG. 13,but any plurality of transistors can be provided. In this case, thelevel of the reference voltage Vref can be set more finely by providingsimilarly controlled sets of transfer gates and fuse elements as well ascontrol signal input terminals in parallel with the plurality oftransistors serving as resistive elements.

[0316]FIG. 14 exemplarily shows the structure using as program elementsthe fuse elements that are disconnected after blow input. However,so-called anti-fuse elements that are rendered conductive after blowinput may alternatively be used. In this case, the same effects can beobtained by providing the transfer gates (TGt1 to TGt3 in FIG. 14) forconducting the tuning test in parallel with the respective anti-fuseelements.

[0317] Note that the adjustment of the data write current as describedin the second embodiment and the modification thereof can be applied notonly to the MRAM device for conducting the data read operation throughthe read gate as described in the first embodiment and the modificationsthereof, but also to an MRAM device having a general structure.

[0318]FIG. 15 shows an example of the structure of the MRAM device forconducting the data read operation without using the read gate.

[0319] The structure of FIG. 15 is different from that of FIG. 2 in thatcolumn selection gates CSG1 to CSGm are provided corresponding to therespective memory cell columns. Each column selection gate couples acorresponding bit line pair BLP to the data I/O line pair DI/OPaccording to the column selection result. For example, the columnselection gate CSG1 couples the data I/O lines IO and /IO of the dataI/O line pair DI/OP to the bit lines BL1 and /BL1 of the correspondingbit line pair BLP1, respectively, according to the voltage on the columnselection line CSL1.

[0320] The data write current +Iw can be supplied to the data I/O linepair DI/OP by the data write circuit 51 b described in connection withFIG. 10. The data write current adjustment circuit 200 or 230 shown inFIGS. 12 and 14 is provided in order to adjust the current amount of thecurrent source 153 in the data write current supply circuit 52 includedin the data write circuit 51 b. Thus, the adjustment of the data writecurrent can be conducted in the same manner.

[0321] The data write current Ip is supplied to the write word line WWLby the word line driver 30. By applying the structure described inconnection with FIG. 13 to the word line driver 30, the adjustment ofthe data write current can be conducted in the same manner as that ofthe second embodiment.

[0322] In the MRAM device having the structure of FIG. 15, a data readcircuit 55 d must supply the sense current Is in the data readoperation.

[0323] The data read circuit 55 d includes current sources 161 and 162for receiving the power supply voltage Vcc to supply a constant currentto respective internal nodes Ns1 and Ns2, an N-type MOS transistor 163electrically coupled between the internal node Ns1 and a node Nr1, anN-type MOS transistor 164 electrically coupled between the internal nodeNs2 and a node Nr2, and an amplifier 165 for amplifying the voltagelevel difference between the internal nodes Ns1 and Ns2 so as to outputread data DOUT.

[0324] The transistors 163 and 164 receive a reference voltage Vrr attheir gates. The respective current amounts supplied from the currentsources 161 and 162 as well as the reference voltage Vrr are setaccording to the amount of the sense current Is. Resistances 166 and 167are provided in order to pull down the internal nodes Ns1 and Ns2 to theground voltage Vss, respectively. The nodes Nr1 and Nr2 are coupled tothe data I/O lines IO and /IO, respectively.

[0325] With such a structure, the data read circuit 55 d supplies thesense current Is to each of the data I/O lines IO and /IO in the dataread operation. The read data DOUT is output according to the respectivevoltage changes produced on the data I/O lines 10 and /IO correspondingto the storage data level in the MTJ memory cell connected theretothrough the column selection gate and the bit line pair.

[0326] Third Embodiment

[0327] In the third embodiment is described the structure in which thebit lines BL and write word lines WWL receiving the data write currentare formed in a plurality of wiring layers.

[0328]FIG. 16 shows the bit line arrangement according to the thirdembodiment of the present invention.

[0329] Referring to FIG. 16, the data write and read operations to andfrom the memory array 10 are conducted through the data I/O line pairDI/OP by the data write circuit 51 b and the data read circuit 55 d,respectively, based on the same structure as that of FIG. 15.

[0330] The bit lines BL1 to BLm, /BL1 to /BLm forming the bit line pairsBLP1 to BLPm, column selection gates CSG1 to CSGm, and column selectionlines CSL1 to CSLm are provided corresponding to the respective memorycell columns.

[0331] The bit lines BL1 to BLm are formed in a wiring layer differentfrom that of the bit lines /BL1 to /BLm. For example, the bit lines BL1to BLm are each formed in a metal wiring layer M3, whereas the bit lines/BL1 to /BLm are each formed in a metal wiring layer M4.

[0332] Each memory cell MC is coupled to one bit line BL of thecorresponding bit line pair. Each dummy memory cell DMC is coupled tothe other bit line /BL of the corresponding bit line pair.

[0333] The read/write control circuit 60 includes equalizing transistors62-1 to 62-m provided corresponding to the respective memory cellcolumns. The equalizing transistor 62 short-circuits the bit lines BLand /BL formed in different metal wiring layers, in response to a bitline equalizing signal BLEQ. The bit line equalizing signal BLEQ isactivated/inactivated in the same manner as that described in the firstembodiment.

[0334] Accordingly, in the data write operation, the data write current+Iw for the bit line pair BLP is supplied to the bit lines BL and /BL inthe selected memory cell column so as to flow in the differentdirections as a reciprocating current. Thus, the structure of the datawrite circuit 51 b including the data write current supply circuit 52can be applied as in the case of the first embodiment.

[0335] As a result, like the first embodiment, a return path of the datawrite current ±Iw can be provided by the equalizing transistor 62.Therefore, the structure for sinking the data write current need not beprovided in the read/write control circuit 60, achieving reduction inlayout area of the peripheral circuitry.

[0336]FIG. 17 shows a first example of the bit line arrangementaccording to the third embodiment.

[0337] Referring to FIG. 17, the write word line WWL is formed in ametal wiring layer M2. The bit line pair BLP has the bit line BL formedin the metal wiring layer M3 and the bit line /BL formed in the metalwiring layer M4. The bit lines BL and /BL are thus formed in thedifferent metal wiring layers so as to interpose the magnetic tunneljunction MTJ therebetween in the vertical direction. As describedbefore, the bit lines BL and /BL are electrically coupled to each otherthrough the equalizing transistor 62 at the end of the memory array 10,so that the data write current flows therethrough.

[0338] Accordingly, the data write current ±Iw in the data writeoperation flows through the bit lines BL and /BL in the differentdirections. Thus, in the magnetic tunnel junction MTJ, the data writemagnetic fields produced by the data write current ±Iw act in such adirection that the respective magnetic fields produced by the bit linesBL and /BL enhance each other. Accordingly, the data write current ±Iwin the data write operation can be reduced. As a result, reduced currentconsumption of the MRAM device, improved reliability resulting from areduced bit line current density, and reduced magnetic field noise inthe data write operation can be achieved.

[0339] On the contrary, in the peripheral portion including other memorycells, the respective magnetic fields produced by the bit lines BL and/BL act in such a direction that cancels each other. As a result, themagnetic field noise in the data write operation can further besuppressed.

[0340]FIG. 18 shows a second example of the bit line arrangementaccording to the third embodiment.

[0341] Referring to FIG. 18, the write word line WWL is provided in themetal wiring layer M3. The bit lines BL and /BL are provided in thedifferent metal wiring layers M2 and M4 so as to interpose the magnetictunnel junction MTJ therebetween in the vertical direction. In thisstructure as well, the magnetic fields produced by the data writecurrent ±Iw act in the same direction as that of FIG. 17. Thus, the sameeffects as those obtained with the structure of FIG. 17 can be obtained.

[0342] Referring back to FIG. 16, in the third embodiment, an externalpower supply voltage Ext.Vcc to the MRAM device 1 is supplied directlyto the data write circuit 51 b and the word line driver 30 foractivating the write word line WWL, i.e., the components for supplyingthe data write current in the data write operation.

[0343] The MRAM device 1 further includes a voltage down converter (VDC)7 for down-converting the external power supply voltage Ext.Vcc toproduce an internal power supply voltage Int.Vcc.

[0344] The internal power supply voltage Int.Vcc produced by the voltagedown converter 7 is supplied to the internal circuitry for conductingthe data read operation and address processing, such as the data readcircuit 55 d, column decoder 25, control circuit 5 and row decoder 20.

[0345] With such a structure, the data write circuit for supplying arelatively large data write current ±Iw as well as the word line driverfor supplying the data write current Ip to the write word line WWL isdriven with the external power supply voltage Ext.Vcc in the data writeoperation. As a result, these data write currents can be suppliedquickly.

[0346] On the other hand, the internal circuitry other than thecircuitry for supplying the data write current is driven with thedown-converted internal power supply voltage Int.Vcc. As a result, powerconsumption in the internal circuitry can be reduced, as well as thereliability corresponding to the shrinking of the device for improvedintegration can be ensured.

[0347] First Modification of Third Embodiment

[0348] Referring to FIG. 19, in the bit line arrangement according tothe first modification of the third embodiment, the bit lines BL and /BLof each bit line pair BLP are provided in the metal wiring layers M3 andM4 so as to cross each other in a region CRS in the memory array 10.

[0349] More specifically, in the region located on the left side of theregion CRS, the bit lines BL and /BL are respectively formed from thewirings provided in the metal wiring layers M3 and M4. In the regionlocated on the light side of the region CRS, however, the bit lines BLand /BL are respectively formed from the wirings provided in the metalwiring layers M4 and M3.

[0350] The wirings corresponding to the bit line BL, which are formed inthe metal wiring layers M3 and M4, are coupled to each other in theregion CRS. Similarly, the wirings corresponding to the bit line /BL,which are formed in the metal wiring layers M3 and M4, are coupled toeach other in the region CRS.

[0351] The bit lines BL and /BL are coupled to the memory cells MC inone of the metal wiring layers. In FIG. 18, the bit lines BL and /BL arecoupled to the memory cells MC in the lower metal wiring layer M3structurally having a smaller distance to the magnetic tunnel junctionMTJ.

[0352] Thus, each of the memory cells MC in the same memory cell columnis coupled to either the bit line BL or /BL. Accordingly, a dummy memorycells DMC coupled to the bit line BL and a dummy memory cell DMC coupledto the bit line /BL are provided in each memory cell column. A dummyread word line DRWL1 is provided in common to the dummy memory cells DMCcoupled to the respective bit lines BL. Similarly, a dummy read wordline DRWL2 is provided in common to the dummy memory cells DMC coupledto the respective bit lines /BL.

[0353] The equalizing transistors 62-1 to 62-m are providedcorresponding to the respective memory cell columns, for coupling thebit lines BL and /BL of the corresponding bit line pair to each other inresponse to the bit line equalizing signal BLEQ.

[0354] With such a structure, a reciprocating current turning around atthe equalizing transistor 62 flows through the bit lines BL and /BL inthe selected memory cell column, whereby the data write operation basedon the folded bit line structure can be conducted.

[0355] Thus, in the bit line arrangement of FIG. 19, the same number ofmemory cells can be coupled to each of the bit lines BL and /BL of eachbit line pair. Therefore, the imbalance of the RC load between the bitlines BL and /BL of the same bit line pair BLP can be corrected.Moreover, since the data read operation based on the folded bit linestructure can be conducted using the dummy memory cells, the data readoperation margin can further be improved.

[0356] Since the structure and the basic operation in reading andwriting the data are otherwise the same as those of FIG. 15, detaileddescription thereof will not be repeated.

[0357] Second Modification of Third Embodiment

[0358] Hereinafter, the structure in which the write word lines WWL areformed in a plurality of metal wiring layers will be described.

[0359]FIG. 20 is a structural diagram illustrating the arrangement ofthe write word lines WWL according to the second modification of thethird embodiment.

[0360] Referring to FIG. 20, the write word line WWL include a sub writeword line WWL1 formed in the metal wiring layer M2 and a sub write wordline WWLu formed in the metal wiring layer M4. The sub write word linesWWL1 and WWLu are provided so as to interpose the magnetic tunneljunction MTJ therebetween in the vertical direction.

[0361]FIGS. 21A and 21B are conceptual diagrams illustrating couplingbetween the sub write word lines forming the same write word line WWL.

[0362] Referring to FIGS. 21A and 21B, the sub write word lines WWLu andWWL1 forming the same write word line WWL are electrically coupled toeach other at the end of the memory array 10. This enables the datawrite current Ip to be supplied as a reciprocating current using the subwrite word lines WWLu and WWL1.

[0363] In FIG. 21A, the sub write word lines WWLu and WWL1 areelectrically coupled to each other through a metal wiring 145 providedin a through hole 144.

[0364] As shown in FIG. 21B, a write word line current control switchTSW formed from a MOS transistor electrically coupled between the subwrite word lines WWLu and WWL1 may be provided in order to short-circuitthe sub write word lines WWLu and WWL1.

[0365] Such a structure enables the data write current Ip to be suppliedto the sub write word lines WWLu and WWL1 of the same write word lineWWL in the opposite directions as a reciprocating current.

[0366] Referring back to FIG. 20, by applying the data write current Ipto the sub write word lines WWL1 and WWLu in the opposite directions,the respective data write magnetic fields produced at the magnetictunnel junction MTJ by the sub write word lines WWLu and WWL1 act in thesame direction, as in the case of FIGS. 16 and 17.

[0367] In the peripheral portion including other memory cells, therespective magnetic fields produced by the sub write word lines WWLu andWWL1 act in such a direction that cancels each other. Thus, with thesame current value, a larger data write magnetic field can be applied tothe magnetic tunnel junction MTJ. As a result, the amount of data writecurrent required to produce a desired data write magnetic field isreduced.

[0368] Thus, reduced current consumption of the MRAM device, improvedoperation reliability resulting from a reduced current density of thewrite word line WWL, and reduced magnetic field noise in the data writeoperation can be realized simultaneously.

[0369] Third Modification of Third Embodiment

[0370] Referring to FIG. 22, in the structure according to the thirdmodification of the third embodiment, the row decoder 20 and write worddrivers WWD1 to WWDn included in the word line driver 30 are provided atone end of the memory array 10 along the row direction. The write worddrivers WWD1 to WWDn are provided corresponding to the respective writeword lines WWL1 to WWLn, for activating the corresponding write wordline WWL according to the decode result of the row decoder 20 so as tosupply the data write current Ip thereto.

[0371] The write word lines WWL are arranged according to the structureshown in FIGS. 20 and 21A. More specifically, the sub write word linesWWLu and WWL1 forming the same write word line WWL are electricallycoupled to each other at the other end of the memory array 10 throughthe metal wiring 145 in the through hole.

[0372] The write word drivers WWD1 to WWDn supply the data write currentIp to one sub write word line WWLu of the corresponding write word lineWWL. The other sub write word line WWL1 forming the same write word lineWWL is coupled to the ground voltage Vss at one end (on the side of thewrite word driver WWD) of the memory array 10.

[0373] Such a structure enables the data write current Ip for the datawrite operation to be supplied to the write word line WWL correspondingto the selected memory cell column as a reciprocating current using thesub write word lines WWLu and WWL1. Note that the connection between thesub write word line WWLu, WWL1 and the write word driver WWD and groundvoltage Vss may be switched so that the sub write word line WWL1 iscoupled to the write word driver WWD and the sub write word line WWLu iscoupled to the ground voltage Vss.

[0374] Fourth Modification of Third Embodiment

[0375] Referring to FIG. 23, in the structure according to the fourthmodification of the third embodiment, the write word drivers WWDcorresponding to the respective write word lines WWL are providedseparately at both ends of the memory array 10. Accordingly, the rowdecoder is also provided separately as a row decoder 20 a for activatingthe write word drivers corresponding to the odd rows and a row decoder20 b for controlling the write word drivers corresponding to the evenrows.

[0376] As described before, the write word driver WWD includes atransistor for supplying the data write current Ip, requiring arelatively large size. Accordingly, providing the write word drivers WWDseparately on both sides of the memory array allows the layout pitchcorresponding to two rows to be utilized for each write word driver WWD.This improves the integration of the write word lines WWL in the rowdirection, allowing for efficient reduction in area of the memory array10.

[0377] Since the structure and operation are otherwise the same as thoseof FIG. 22, detailed description thereof will not be repeated.

[0378] Fifth Modification of Third Embodiment

[0379] Referring to FIG. 24, in the structure according to the fifthmodification of the third embodiment, the sub write word lines WWLu toWWL1 forming the same write word line WWL are electrically coupled toeach other by a corresponding write word line current control switch TSWat one end (on the side of the row decoder 20) of the memory array 10.The write word line current control switches TSW are providedcorresponding to the respective memory cell rows.

[0380]FIG. 24 exemplarily shows the write word line current controlswitches TSW1 and TSW2 corresponding to the write word lines WVVWL1 andWWL2, respectively. The write word line current control switch TSW isturned ON under the control of the row decoder 20 in response toselection of the corresponding memory cell row.

[0381] The sub write word lines WWLu and WWL1 forming the same writeword line WWL are respectively coupled to the power supply voltage Vccand the ground voltage Vss at the other end of the memory array 10.Accordingly, the write word line current control switch TSW is turned ONbased on the row selection result, whereby the reciprocating data writecurrent Ip can be supplied to the sub write word lines WWLu and WWL1 ofthe corresponding write word line WWL. Thus, the same effects as thoseof the third and fourth modifications of the third embodiment can beobtained.

[0382] During the OFF period of the corresponding write word linecurrent control switch TSW, the sub write word lines WWLu and WWL1 arerespectively set to the power supply voltage Vcc and the ground voltageVss. Accordingly, the voltage on the write word line WWL can be restoredrapidly to the stand-by state or non-selected state after the operationof selecting the write word line WWL is completed.

[0383]FIG. 24 exemplarily shows the structure in which the sub writeword lines WWLu and WWL1 are respectively coupled to the power supplyvoltage Vcc and the ground voltage Vss at the other end of the memoryarray 10. However, this connection may be switched such that the subwrite word lines WWLu and WWL1 are respectively coupled to the groundvoltage Vss and the power supply voltage Vcc.

[0384] More specifically, since the reciprocating data write current Ipis supplied in the data write operation, the write word line WWL isincreased in length. However, the write word line WWL is divided intothe sub write word lines WWLu and WWL1, which are restored to therespective prescribed voltage levels. Such a structure enables the writeword line WWL to be restored rapidly to the stand-by state or thenon-selected state while obtaining the effects resulting from supplyingthe data write current as a reciprocating current.

[0385] Note that, in the third to fifth modifications of the thirdembodiment, at least one of the dummy write word lines DWWL1, DWWL2 andwrite word drivers DWWD1, DWWD2 and the write word line current controlswitches DTSW1, DTSW2 is provided also for the dummy memory cells MCthat originally do not relate to the data write operation. The dummywrite word lines DWWL1, DWWL2, the write word drivers DWWD1, DWWD2, andthe write word line current control switches DTSW1, DTSW2 each has thesame structure as that provided for the memory cell MC.

[0386] However, since the data write current need not be supplied to thedummy memory cells DMC, the input of the write word drivers DWWD1 andDWWD2 corresponding to the dummy memory cells is fixed to the powersupply voltage Vcc. Accordingly, the dummy write word line DWWL1, DWWL2is always retained in the inactive state (ground voltage Vss), and acurrent is not applied thereto. Moreover, the gate of the N-type MOStransistor forming the corresponding write word line current controlswitch DTSW is fixed to the ground voltage Vss, so that the N-type MOStransistor is retained in the OFF state.

[0387] Providing the write word lines WWL in the memory array 10 exceptfor the region corresponding to the dummy memory cells DMC causes lackin continuity in terms of the shape. This may possibly result indefective shape during production of the MRAM device. In order to avoidsuch a problem, the write word lines, write word drivers, and peripheralcircuitry thereof (write word line current control switches TSW in FIG.24) each having the same structure as that provided for the regularmemory cells MC can be provided also for the dummy memory cells DMC forwhich the data write operation is not required.

[0388] Note that it is also possible to combine the arrangement of thebit lines and write word lines according to the third embodiment and themodifications thereof with each or both of the first and secondembodiments. In this case, the data write circuit and the data readcircuit need only be structured as described in the first and secondembodiments and the modifications thereof.

[0389] Fourth Embodiment

[0390] Referring to FIG. 25, an MTJ memory cell MCD according to thefourth embodiment includes a magnetic tunnel junction MTJ and an accessdiode DM, as in the structure of FIG. 90. The MTJ memory cell MCD isdifferent from that of FIG. 90 in that the read word line RWL and thewrite word line WWL are separately provided. The bit line BL extends insuch a direction that crosses the write word lines WWL and the read wordline RWL, and is electrically coupled to the magnetic tunnel junctionMTJ.

[0391] The access diode DM is coupled between the magnetic tunneljunction MTJ and the read word line RWL. Herein, the direction from themagnetic tunnel junction MTJ toward the read word line RWL is a forwarddirection. The write word line WWL is provided near the magnetic tunneljunction MTJ without being connected to the bit line BL, read word lineRWL and access diode DM.

[0392] Referring to FIG. 26, an N-type region (N-well, n⁺ diffusionregion, or the like) NWL formed at the semiconductor main substrate SUBcorresponds to the cathode of the access diode DM. In the case where theMTJ memory cells are arranged in rows and columns on the semiconductorsubstrate, the N-type regions NWL for the MTJ memory cells in the samerow may be electrically coupled to each other. Thus, the couplingbetween the access diode DM and the read word line RWL as shown in FIG.25 can be implemented without providing the read word line RWL.

[0393] A P-type region PAR formed at the N-type region NWL correspondsto the anode of the access diode DM. The P-type region PAR iselectrically coupled to the magnetic tunnel junction MTJ through abarrier metal 140 and a metal film 150.

[0394] The write word line WWL and the bit line BL are respectivelyprovided in the metal wiring layers M1 and M2. The bit line BL iscoupled to the magnetic tunnel junction MTJ.

[0395]FIG. 27 is a timing chart illustrating the read and writeoperations from and to the MTJ memory cell MCD.

[0396] Referring to FIG. 27, in the data write operation, the voltage onthe read word line RWL, i.e., the N-type region NWL, is set to H level(power supply voltage Vcc). In the data read operation, no current flowthrough the read word line RWL.

[0397] The power supply voltage Vcc is applied to the write word lineWWL corresponding to the selected memory cell, so that the data writecurrent Ip flows therethrough. According to the write data level, thebit line BL is set to the power supply voltage Vcc at its one end and tothe ground voltage Vss at the other end. Thus, the data write current±Iw corresponding to the write data level can be supplied to the bitline BL.

[0398] With the data write currents Ip and ±Iw thus supplied, the datais written to the MTJ memory cell. In this case, the read word line RWLis set to the power supply voltage Vcc, so that the access diode DM isreliably turned OFF in the data write operation. As a result, the datawrite operation can be conducted more stably as compared to the case ofthe MTJ memory cell shown in FIG. 90.

[0399] Hereinafter, the data read operation will be described.

[0400] Before the data read operation, the bit lines BL are prechargedto the ground voltage Vss.

[0401] The read word line RWL corresponding to the memory cell MCD to beread is driven to the active state (L level: ground voltage Vss) in thedata read operation. In response to this, the access diode DM is biasedin the forward direction. Thus, the sense current Is is supplied to apath formed from the bit line BL, magnetic tunnel junction MTJ, accessdiode DM and read word line RWL (ground voltage Vss), enabling the dataread operation.

[0402] More specifically, a voltage change produced on the bit line BLis amplified with the sense amplifier Is, so that the storage data inthe magnetic tunnel junction MTJ can be read.

[0403] Note that, as shown in FIG. 26, the distance between the bit lineBL and the magnetic tunnel junction MTJ is smaller than that between thewrite word line WWL and the magnetic tunnel junction MTJ. Therefore,with the current amount being the same, the magnetic field produced bythe data write current flowing through the bit line BL is larger thanthat produced by the data write current flowing though the write wordline WWL.

[0404] In order to apply the data write magnetic fields of approximatelythe same strength to the magnetic tunnel junction MTJ, a larger datawrite-current must be supplied to the write word line WWL than to thebit line BL. The bit line BL and the write word line WWL are formed inthe metal wiring layers in order to reduce the electrical resistancevalue. However, an excessive current density in the wirings may possiblycause disconnection or short-circuit of the wirings due to theelectromigration phenomenon, thereby possibly degrading the operationreliability. It is therefore desirable to suppress the current densityof the wirings receiving the data write current.

[0405] Accordingly, in the case where the MTJ memory cell MCD shown inFIG. 25 is provided on the semiconductor substrate, the cross sectionalarea of the write word line WWL is made larger than that of the bit lineBL located closer to the magnetic tunnel junction MTJ, in order tosuppress the current density of the write word line WWL to which alarger data write current must be supplied. Thus, improved reliabilityof the MRAM device can be achieved.

[0406] For the improved reliability, it is also effective to form ametal wiring located farther from the magnetic tunnel junction MTJ andthus requiring a larger data write current to be supplied thereto (i.e.,the write word line WWL in FIG. 26), from a highlyelectromigration-resistant material. For example, in the case where theother metal wirings are formed from an aluminum alloy (Al alloy), themetal wirings that may be subjected to electromigration may be formedfrom copper (Cu).

[0407]FIG. 28 is a conceptual diagram showing the memory array structurehaving the MTJ memory cells MCD arranged in rows and columns.

[0408] Referring to FIG. 28, with the MTJ memory cells arranged in rowsand columns on the semiconductor substrate, a highly integrated MRAMdevice can be realized. FIG. 28 shows the case where the MTJ memorycells MCD are arranged in n rows by m columns.

[0409] As described before, the bit line BL, write word line WWL andread word line RWL must be provided for each MTJ memory cell MCD.Accordingly, n write word lines WWL1 to WWLn, n read word lines RWL1 toRWLn, and m bit lines BL1 to BLm are provided for the MTJ memory cellsarranged in n rows by m columns.

[0410]FIG. 29 shows the memory array structure in which the MTJ memorycells MCD arranged in rows and columns share the write word lines WWL.

[0411] Referring to FIG. 29, the read word lines RWL and write wordlines WWL provided for the MTJ memory cells MCD having the structure ofFIG. 25 extend in the row direction. Each write word line WWL is sharedbetween adjacent memory cells.

[0412] For example, the MTJ memory cell coupled to the read word lineRWL1 and the MTJ memory cell coupled to the read word line RWL2 sharethe same write word line WWL1.

[0413] Such sharing of the write word lines WWL can reduce the number ofwrite word lines WWL in the whole memory array. Thus, improvedintegration of the MTJ memory cells in the memory array as well asreduced chip area can be achieved.

[0414] Such a reduced number of write word lines WWL also ensures thewiring pitch of the write word lines WWL in the metal wiring layer M1shown in FIG. 26. Accordingly, an increased wiring width of the writeword line WWL can be readily obtained. This makes it easy to make thecross sectional area of the write word line WWL larger that of the bitline BL located closer to the magnetic tunnel junction MTJ. As a result,the electromigration can be suppressed, whereby improved reliability ofthe MRAM device can be readily achieved.

[0415] Moreover, the MTJ memory cells MCD according to the fourthembodiment may be used in the first to third embodiments as memory cellsMC arranged in the memory array 10.

[0416] Modification of Fourth Embodiment

[0417] Such sharing of the wirings can be applied to the conventionalMTJ memory cell having the structure shown in FIG. 90.

[0418]FIG. 30 shows the arrangement of the MTJ memory cells according tothe modification of the fourth embodiment.

[0419]FIG. 30 shows a memory array integrating MTJ memory cells MCD′having the structure shown in FIG. 90.

[0420] Referring to FIG. 30, in the memory array having the MTJ memorycells MCD′ arranged in rows and columns according to the modification ofthe fourth embodiment, adjacent memory cell MCD′ in the column directionshare the same word line WL. For example, the memory cell MCD′ of thefirst memory cell row and the memory cell MCD′ of the second memory cellrow share the same word line WL1.

[0421] Such a structure reduces the number of word lines WL in theentire memory array, whereby improved integration of the MTJ memorycells as well as reduced chip area can be achieved.

[0422] Referring back to FIG. 91, in the MTJ memory cell of FIG. 90 aswell, the distance between the word line WL and the magnetic tunneljunction MTJ is larger than that between the bit line BL and themagnetic tunnel junction MTJ. Accordingly, a larger data write currentmust be supplied to the word line WL. In order to ensure the operationreliability, it is important to reduce the current density on the wordline WL in such an MTJ memory cell.

[0423] In the modification of the fourth embodiment, the wiring pitch ofthe word lines WL requiring a larger data write current can be readilyensured. Accordingly, the current density on the word line WL issuppressed, whereby the improved reliability of the MRAM device can beachieved. As described in the fourth embodiment, the operationreliability of the MRAM device can further be improved by using a higherelectromigration-resistant material to form the wiring to which a largerdata rite current must be supplied.

[0424] Fifth Embodiment

[0425] In the fifth and the following embodiments, improved integrationof the memory array is described for the case where the read word lineRWL and the write word line WWL extend in different directions.

[0426] Referring to FIG. 31, in an MRAM device 2 according to the fifthembodiment of the present invention, the read word lines RWL and thewrite word lines WWL respectively extend in the row and columndirections on the memory array 10.

[0427] The bit lines are correspondingly divided into read bit lines RBLand write bit lines WBL, so that the read bit lines RBL and the writebit lines WBL respectively extend in the column and row directions onthe memory array 10.

[0428] Accordingly, the MRAM device 2 is different from the MRAM device1 of FIG. 1 in that the word line driver 30 is divided into a read wordline driver 30 r and a write word line driver 30 w.

[0429] The read/write control circuits 50, 60 are also divided intowrite control circuits 50 w, 60 w provided adjacent to the memory array10 in the row direction, and a read control circuit 50 r.

[0430] Since the structure and operation are otherwise the same as thoseof the MRAM device 1, detailed description thereof will not be repeated.

[0431] Referring to FIG. 32, in the fifth embodiment, the read word lineRWL, write word line WWL, write bit line WBL and read bit line RBL areprovided for the MTJ memory cell having the magnetic tunnel junction MTJand access transistor ATR. A MOS transistor, which is a field effecttransistor formed on the semiconductor substrate SUB, is typically usedfor the access transistor ATR.

[0432] The access transistor ATR has its gate coupled to the read wordline RWL. The access transistor ATR is turned ON (actuated) in responseto activation of the read word line RWL to the selected state (H level:power supply voltage Vcc), forming a current path including the magnetictunnel junction MTJ. On the other hand, when the read word line RWL isinactivated to the non-selected state (L level: ground voltage Vss), theaccess transistor ATR is turned OFF. Therefore, the current pathincluding the magnetic tunnel junction MTJ is not formed.

[0433] Thus, by providing the read word line RWL and the write word lineWWL extending perpendicularly to each other, the read word line driver30 r and the write word line driver 30 w can be provided separately.

[0434] The write word line WWL and the write bit line WBL extendperpendicular to each other near the magnetic tunnel junction MTJ.

[0435] The write word line WWL can be provided independently withoutbeing coupled to other portions of the MTJ memory cell. Accordingly, thewrite word line WWL can be arranged for improved magnetic coupling withthe magnetic tunnel junction MTJ. Thus, the data write current Ipflowing through the write word line WWL can be suppressed.

[0436] Since the respective activation of the read word line RWL and thewrite word line WWL is controlled independently in the data read andwrite operations, their respective drivers can be originally designed asindependent drivers. Accordingly, the write word line driver 30 w andthe read word line driver 30 r each having a reduced size can beseparately provided in different regions adjacent to the memory array10. As a result, the freedom of layout is improved, whereby the layoutarea, i.e., the chip area of the MRAM device, can be reduced.

[0437] The magnetic tunnel junction MTJ is electrically coupled betweenthe read bit line RBL and the access transistor ATR. Accordingly, in thedata read operation, the voltage level on the write bit line WBL thatrequires no current supply is set to the ground voltage Vss. As aresult, a current path is formed by the read bit line RBL, magnetictunnel junction MTJ, access transistor ATR and write bit line WBL(ground voltage Vss) in response to turning-ON of the access transistorATR. In response to the sense current Is supplied to this current path,a voltage change corresponding to the storage data level in the magnetictunnel junction MTJ is produced on the read bit line RBL, whereby thestorage data can be read.

[0438] In the data write operation, the data write current is suppliedto each of the write word line WWL and the write bit line WBL. When thesum of the magnetic fields produced by these data write currents reachesa fixed magnetic field, i.e., the region beyond the asteroidcharacteristic line shown in FIG. 86, the storage data is written to themagnetic tunnel junction MTJ.

[0439] Hereinafter, the data write and read operations to and from theMTJ memory cell according to the fifth embodiment will be described withreference to FIG. 33.

[0440] First, the data write operation will be described.

[0441] According to the column selection result of the column decoder25, the write word line driver 30 w drives the voltage on the write wordline WWL corresponding to the selected column to the selected state (Hlevel). In the non-selected columns, the voltage levels on the writeword lines WWL are retained in the non-selected state (L level). Sinceeach write word line WWL is coupled to the ground voltage Vss by theword line current control circuit 40, the data write current Ip flowsthrough the write word line WWL of the selected column.

[0442] In the data write operation, the read word lines RWL are retainedin the non-selected state (L level). In the data write operation, theread control circuit 50 r does not supply the sense current Is, butprecharges the read bit lines RBL to the high voltage state (Vcc). Sincethe access transistors ATR are retained in the OFF state, no currentflows through the read bit lines RBL in the data write operation.

[0443] The write control circuits 50 w and 60 w control the voltage onthe write bit line WBL at both ends of the memory array 10, therebyproducing a data write current in the direction corresponding to thelevel of the write data DIN.

[0444] For example, in order to write the storage data “1”, the bit linevoltage on the side of the write control circuit 60 w is set to the highvoltage state (power supply voltage Vcc), and the bit line voltage onthe opposite side, i.e., on the side of the write control circuit 50 w,is set to the low voltage state (ground voltage Vss). As a result, thedata write current +Iw flows through the write bit line WBL from thewrite control circuit 60 w toward 50 w.

[0445] In order to write the storage data “0”, the bit line voltages onthe side of the write control circuits 50 w and 60 w are respectivelyset to the high and low voltage states, whereby the data write current-Iw flows through the write bit line WBL from the write control circuit50 w toward 60 w. At this time, the data write current ±Iw isselectively applied to the write bit line WBL corresponding to theselected row, according to the row selection result of the row decoder20.

[0446] By setting the directions of the data write currents Ip and ±Iwin this way, one of the data write currents +Iw and −Iw of the oppositedirections is selected according to the storage data level “1” or “0” tobe written, and the data write current Ip on the write word line WWL canbe made to flow in the fixed direction regardless of the data level.Thus, the data write current Ip flowing through the write word line WWLcan be always kept in the fixed direction. As a result, the structure ofthe word line current control circuit 40 can be simplified, as describedbefore.

[0447] Next, the data read operation will be described.

[0448] In the data read operation, the write word lines WWL are retainedin the non-selected state (L level), and the voltage level thereof isfixed to the ground voltage Vss by the word line current control circuit40. In the data read operation, the write control circuits 50 w and 60 wdiscontinue supply of the data write current to the write bit line WBL,and set the write bit lines WBL to the ground voltage Vss.

[0449] The read word line driver 30 r drives the read word line RWLcorresponding to the selected row to the selected state (H level),according to the row selection result of the row decoder 20. In thenon-selected rows, the voltage levels on the read word lines RWL areretained in the non-selected state (L level). In the data readoperation, the read control circuit 50 r supplies the read bit line RBLof the selected column with a fixed amount of sense current Is forconducting the data read operation. The read bit lines RBL areprecharged to the high voltage state (Vcc) before the data readoperation. Therefore, when the access transistor ATR is turned ON inresponse to activation of the read word line RWL, a current path of thesense current Is is formed within the MTJ memory cell, whereby a voltagechange (drop) corresponding to the storage data is produced on the readbit line RBL.

[0450] It is now assumed in FIG. 33 that the fixed magnetic layer FL andthe free magnetic layer VL have the same magnetic field direction whenthe storage data level is “1”. In this case, the read bit line RBL has asmall voltage change ΔV1 when the storage data is “1”, and has a voltagechange ΔV2 larger than ΔV1 when the storage data is “0”. The storagedata of the MTJ memory cell can be read by sensing the differencebetween the voltage drops ΔV1 and ΔV2.

[0451] In the data write operation, the read bit lines RBL are set tothe same voltage as the precharge voltage for the data read operation,i.e., the power supply voltage Vcc. This enables the prechargingoperation for the read data operation to be conducted efficiently,increasing the data read operation speed. Note that, when the prechargevoltage of the read bit lines RBL is set to the ground voltage Vss, theread bit lines RBL need only be set to the ground voltage Vss in thedata write operation.

[0452] Similarly, the write bit lines WBL, which must be set to theground voltage Vss in the data read operation, can be set to the groundvoltage Vss after the data write operation, in order to increase thedata read speed.

[0453] Referring to FIG. 34, in the MTJ memory cell according to thefifth embodiment, the access transistor ATR is formed in a p-type regionPAR of the semiconductor substrate SUB. The write bit line WBL is formedin a first metal wiring layer M1 so as to be electrically coupled to oneof the source/drain regions, i.e., 110, of the access transistor ATR.The other source/drain region 120 is electrically coupled to themagnetic tunnel junction MTJ through a metal wiring provided in thefirst metal wiring layer M1, a barrier metal 140 and a metal film 150formed in a contact hole.

[0454] The read bit line RBL is provided in a third metal wiring layerM3 so as to be electrically coupled to the magnetic tunnel junction MTJ.The write word line WWL is provided in a second metal wiring layer M2.The write word line WWL can be independently provided without beingcoupled to other portions of the MTJ memory cell. Therefore, the writeword line WWL can be arbitrarily arranged so as to enhance the magneticcoupling with the magnetic tunnel junction MTJ.

[0455] With such a structure, the read word line RWL and the write wordline WWL are provided for the MTJ memory cell so as to extendperpendicularly to each other, and the read word line driver 30 r andwrite word line driver 30 w respectively corresponding to the read wordline RWL and write word line WWL are independently provided. Thus, thefreedom of layout can be improved. Moreover, a word line drive currentis prevented from being excessively increased in the data readoperation, whereby generation of undesirable magnetic noise can beprevented.

[0456] Referring to FIG. 35, in the memory array 10 according to thefifth embodiment, the memory cells MC having the structure of FIG. 32are arranged in rows and columns. The read word lines RWL and the writeword lines WWL respectively extend in the row and column directions. Theread bit lines RBL and the write bit lines WBL respectively extend inthe column and row directions. The read bit lines and the write bitlines are also generally denoted with RBL and WBL, respectively, and aspecific read bit line and write bit line are denoted with, e.g., RBL1and WBL1.

[0457] The word line current control circuit 40 couples each write wordline WWL to the ground voltage Vss. Thus, in the data read and writeoperations, the voltage and current on the write word line WWL can becontrolled as shown in FIG. 33.

[0458] Adjacent memory cells in the row direction share the read bitline RBL, and adjacent memory cells in the column direction share thewrite bit line WBL.

[0459] For example, the memory cell group of the first and second memorycell columns shares the same read bit line RBL1, and the memory cellgroup of the third and fourth memory cell columns shares the same readbit line RBL2. Moreover, the memory cell group of the second and thirdmemory cell rows shares the write bit line WBL2. In the following memorycell rows and columns as well, the read bit lines RBL and the write bitlines WBL are arranged similarly.

[0460] If the data is to be read from or written to a plurality ofmemory cells MC of the same read bit line RBL or write bit line WBL,data collision occurs. Accordingly, the memory cells MC are arrangedalternately.

[0461] With such a structure, the pitches of the read bit lines RBL andthe write bit lines WBL in the memory array 10 can be widened. As aresult, the memory cells MC can be efficiently arranged, wherebyimproved integration of the memory array 10 as well as reduced chip areaof the MRAM device can be achieved.

[0462] Hereinafter, the peripheral circuitry for supplying the sensecurrent Is and the data write current +Iw will be described.

[0463] Column selection for the data read operation is conducted usingthe read column selection lines RCSL and the read column selection gatesRCSG, both provided corresponding to the respective read bit lines RBL.FIG. 35 exemplarily shows the read column selection lines RCSL1, RCSL2and the read column selection gates RCSG1, RCSG2, which are providedcorresponding to the respective read bit lines RBL1 and RBL2.

[0464] In the data read operation, the column decoder 25 activates oneof the plurality of read column selection lines RCSL to the selectedstate (H level) according to the column selection result.

[0465] The read column selection gate RCSG connects a read data line RDLto the corresponding read bit line RBL according to the voltage on thecorresponding read column selection line RCSL. A data read circuit 55 esupplies the sense current Is to the read data line RDL.

[0466] Referring to FIG. 36, the data read circuit 55 e is differentfrom the data read circuit 55 d of FIG. 15 in that the data read circuit55 e supplies the sense current Is only to the node Nr1. Accordingly,the transistor 164 shown in FIG. 15 is eliminated, and the referencevoltage Vref is applied only to the gate of the transistor 163.

[0467] The data read circuit 55 e senses the level of the read data DOUTbased on the comparison between a voltage drop caused by the sensecurrent Is and a reference voltage drop ΔVr. Provided that the data linehas a voltage drop ΔVh when the H-level data is read, and has a voltagedrop ΔVl when the L-level data is read, ΔVr is set to an intermediatevalue of ΔVh and ΔVl.

[0468] Accordingly, in the data read circuit 55 e, the resistance valueof the resistance 167 is set so that the node Ns2 has a voltage level(Vcc−ΔVr).

[0469] Referring back to FIG. 35, the sense current Is is selectivelysupplied to the read bit line RBL corresponding to the column selectionresult through the read column selection gate RCSG.

[0470] According to the row selection result, the read word line driver30 r selectively activates the read word line RWL. Thus, the sensecurrent Is can be supplied to the MTJ memory cell corresponding to theselected memory cell row.

[0471] On the other hand, column selection for the data write operationis conducted in response to selective activation of the write word lineWWL by the write word line driver 30 w according to the column selectionresult. Each write word line WWL is coupled to the ground voltage Vss inthe word line current control circuit 40.

[0472] The write bit lines WBL are provided corresponding to therespective memory cell rows so as to extend perpendicularly to the writeword lines WWL. Accordingly, row selection for the data write operationis conducted using write row selection lines and write row selectiongates, which are provided corresponding to the respective write bitlines WBL.

[0473]FIG. 35 exemplarily shows the write row selection lines WRSL1,WRSL2 and the write row selection gates WRSG1, WRSG2, which are providedcorresponding to the write bit lines WBL1, WBL2. Hereinafter, the writerow selection lines and the write row selection gates are also generallydenoted with WRSL and WRSG, respectively.

[0474] The write row selection gate WRSG is electrically coupled betweenthe corresponding write bit line WBL and a write data line WDL, and isturned ON/OFF according to the voltage on the corresponding write rowselection line WRSL.

[0475] The read/write control circuit 60 includes bit line currentcontrol transistors provided corresponding to the respective write bitlines WBL. FIG. 35 exemplarily shows the bit line current controltransistors 63-1, 63-2 provided corresponding to the write bit linesWBL1, WBL2, respectively. Hereinafter, the bit line current controltransistors are also generally denoted with 63.

[0476] The bit line current control transistor 63 is electricallycoupled between the corresponding write bit line WBL and a write dataline /WDL, and is turned ON/OFF according to the voltage on thecorresponding write row selection line WRSL.

[0477] The data write circuit 51 b shown in FIG. 7 supplies the datawrite current ±Iw to the write data lines WDL and /WDL. Thus, the datawrite current +Iw can be supplied to the write bit line WBLcorresponding to the selected memory cell row, according to the rowselection result of the row decoder 20.

[0478] The read/write control circuit 60 further includes prechargingtransistors provided corresponding to the respective read bit lines RBL,and write bit line voltage control transistors provided corresponding tothe respective write bit lines WBL.

[0479]FIG. 35 exemplarily shows the precharging transistors 64-1, 64-2provided corresponding to the read bit lines RBL1, RBL2, and the writebit line voltage control transistors 65-1, 65-2 provided correspondingto the write bit lines WBL, WBL2, respectively. Hereinafter, theplurality of write bit line voltage control transistors are alsogenerally denoted with 65.

[0480] Each write bit line voltage control transistor 65 is turned ON inthe data read operation to couple the corresponding write bit line WBLto the ground voltage Vss in order to ensure the current path of thesense current Is. In the operation other than the data read operation,each write bit line voltage control transistor 65 is turned OFF, so thateach write bit line WBL is disconnected from the ground voltage Vss.Since the operation of the precharging transistor 64 is the same as thatdescribed in connection with FIG. 2, description thereof will not berepeated.

[0481] With such a structure, in the data write operation, the datawrite current ±Iw can be supplied to the write bit line WBLcorresponding to the selected memory cell row through the path formedfrom the write data line WDL, write row selection gate WRSG, write bitline WBL, bit line current control transistor 63 and write data line/WDL. Note that it is possible to control the direction of the datawrite current ±Iw by setting the voltage on the write data line WDL,/WDL in the same manner as that of the write data bus WDB, /WDB of thefirst embodiment. Accordingly, like the first embodiment, the structureof the peripheral circuitry associated with the data write operation,i.e., the write control circuit 50 w and 60 w can be simplified.

[0482] Thus, the data write and read operations as shown in FIG. 33 canbe conducted even in the structure in which the read word lines RWL andthe write word lines WWL extend perpendicularly to each other and thewrite bit line WBL and the read bit line RBL are shared between adjacentmemory cells.

[0483] With such a structure, the pitches of the write bit lines WBL andthe read bit lines RBL in the memory array 10 can be widened. As aresult, the memory cells MC can be efficiently arranged, wherebyimproved integration of the memory array 10 as well as reduced chip areaof the MRAM device can be achieved.

[0484] Such the widened pitch of the write bit lines WBL ensure anincreased line width of the write bit lines WBL. Accordingly, thefollowing effects can further be obtained.

[0485] As described before, in the data write operation, the data writecurrent must be supplied to both the write bit line WBL and the writeword line WWL.

[0486] As shown in FIG. 34, in the MTJ memory cell structure accordingto the fifth embodiment, the distance between the write bit line WBL andthe magnetic tunnel junction MTJ in the vertical direction is largerthan that between the write word line WWL and the magnetic tunneljunction MTJ. Accordingly, in the data write operation, a larger currentmust be supplied to the write bit line WBL that is located farther fromthe magnetic tunnel junction MTJ.

[0487] However, the write bit line WBL is shared between adjacent memorycell columns. Therefore, the write bit line WBL can be arranged usingthe space for two memory cell rows, whereby the line width of each writebit line WBL can be increased. Thus, a line width at least larger thanthat of the write word line WWL, i.e., a larger cross-sectional area, ofthe write bit line WBL can be ensured. As a result, the current densityof the write word line WWL is suppressed.

[0488] The reliability of the MRAM device can thus be improved bysharing one of the wirings requiring the data write current supply,i.e., the wiring that is structurally located farther from the magnetictunnel junction MTJ, between adjacent memory cells.

[0489] For improved reliability, it is also effective to form a metalwiring having a large distance to the magnetic tunnel junction MTJ (thewrite bit line WBL in FIG. 34) from a highly electromigration-resistantmaterial. For example, in the case where the other metal wirings areformed from an aluminum alloy (Al alloy), the metal wirings that maypossibly be subjected to electromigration may be formed from copper(Cu).

[0490] First Modification of Fifth Embodiment

[0491] Referring to FIG. 37, in the memory array according to the firstmodification of the fifth embodiment, adjacent memory cells share thesame write word line WWL. For example, the memory cell group of thefirst and second memory cell columns shares a single write word lineWWL1. In the following memory cell columns as well, the write word linesWWL are arranged similarly.

[0492] In order to conduct the data write operation normally, aplurality of memory cells MC must not be present at the intersection ofthe same write word line WWL and the same write bit line WBL.Accordingly, the memory cells MC are arranged alternately.

[0493] Since the structure of the peripheral circuitry associated withthe data read and write operations through the read bit line RBL andwrite bit line WBL, as well as the memory cell operation in reading andwriting the data are the same as those of the fifth embodiment, detaileddescription thereof will not be repeated.

[0494] With such a structure, the pitch of the write word lines WWL inthe memory array 10 can be widened. As a result, the memory cells MC canbe efficiently arranged, whereby improved integration of the memoryarray 10 as well as reduced chip area of the MRAM device can beachieved.

[0495] Second Modification of Fifth Embodiment

[0496] Referring to FIG. 38, the memory array according to the secondmodification of the fifth embodiment is different from that of the firstmodification of the fifth embodiment in that adjacent memory cells inthe column direction also share the same read word line RWL. Forexample, the memory cell group of the first and second memory cell rowsshares the same read word line RWL1. In the following memory cell rowsas well, the read word lines RWL are arranged similarly.

[0497] In order to conduct the data read and write operations normally,a plurality of memory cells MC selected by a single read word line RWLor write word line WWL must not be simultaneously coupled to the sameread bit line RBL or write bit line WBL. Accordingly, the read bit lineRBL and the write bit line WBL are provided in every memory cell columnand every memory cell row, respectively, and the memory cells MC arearranged alternately.

[0498] Since the structure of the other portions and the memory celloperation in reading and writing the data are the same as those of thefifth embodiment, detailed description thereof will not be repeated.

[0499] With such a structure, the pitches of the read word lines RWL andwrite word lines WWL in the memory array 10 can be widened. As a result,the memory cells MC can be more efficiently arranged, whereby improvedintegration of the memory array 10 as well as reduced chip area of theMRAM device can be achieved.

[0500] Third Modification of Fifth Embodiment

[0501] Referring to FIG. 39, for the memory cells having the structureof the fifth embodiment and arranged in rows and columns, the folded bitline structure is realized in every set of adjacent two memory cellcolumns, using corresponding two read bit lines RBL. For example, a readbit line pair can be formed from the read bit lines RBL1 and RBL2respectively corresponding to the first and second memory cell columns.In this case, the read bit line RBL2 is also referred to as read bitline /RBL1 because it is complementary to the read bit line RBL1.

[0502] Hereinafter, one read bit line of each read bit line pair thatcorresponds to an odd memory cell column is also generally referred toas read bit line RBL, and the other read bit line that corresponds to aneven memory cell column is also generally referred to as read bit line/RBL.

[0503] A read column selection line is provided for every read bit linepair, i.e., every set of memory cell columns. Accordingly, two readcolumn selection gates RCSG corresponding to the same set are turnedON/OFF in response to the common read column selection line RCSL.

[0504] For example, the read column selection gates RCSG1 and RCSG2corresponding to the first and second memory cell columns operate inresponse to the common read column selection line RCSL1. The read columnselection gates RCSG1, RCSG3, . . . corresponding to the read bit linesRBL of the odd columns are each electrically coupled between thecorresponding read bit line RBL and the read data line RDL. The readcolumn selection gates RCSG2, RCSG4, . . . corresponding to the read bitlines /RBL of the even columns are each electrically coupled between thecorresponding read bit line /RBL and a read data line /RDL.

[0505] In response to the read column selection line RCSL activatedaccording to the column selection result, corresponding two read columnselection gates RCSG are turned ON. As a result, the read bit lines RBLand /RBL of the read bit line pair corresponding to the selected memorycell column are electrically coupled to the read data lines RDL and /RDLof the read data line pair, respectively.

[0506] Moreover, the same precharging transistors 64 as those describedin connection with FIG. 35 are provided corresponding to the respectiveread bit lines RBL and /RBL. As described before, the prechargingtransistors 64 are turned OFF in the data read operation.

[0507] As a result, the sense current Is is supplied from the data readcircuit 55 d to each of the read bit lines RBL and /RBL corresponding tothe selected memory cell column through the read data lines RDL and/RDL. Since the structure of the data read circuit 55 d has beendescribed in connection with FIG. 15, detailed description thereof willnot be repeated.

[0508] Accordingly, the data read operation is conducted using the samedummy memory cells DMC as those of the first embodiment each capable ofbeing selectively coupled to either the read bit line RBL or /RBL. Thus,the data read margin can be ensured based on the so-called folded bitline structure.

[0509] Similarly, the folded bit line structure is realized in every setof adjacent two memory cell rows, using corresponding two write bitlines WBL. For example, a write bit line pair can be formed from thewrite bit lines WBL1 and WBL2 respectively corresponding to the firstand second memory cell rows. In this case, the write bit line WBL2 isalso referred to as write bit line /WBL1 because it is complementary tothe write bit line WBL1.

[0510] In the following memory cell columns as well, the read bit linesRBL and the write bit lines WBL are similarly arranged so as to form aread bit line pair and a write bit line pair in every set of memory cellcolumns and rows, respectively.

[0511] One write bit line of each write bit line pair that correspondsto an odd memory cell row is also generally referred to as write bitline WBL, and the other write bit line that corresponds to an evenmemory cell row is also generally referred to as write bit line /WBL.Thus, the data write operation can be conducted based on the so-calledfolded bit line structure.

[0512] The write row selection line WRSL is provided for every write bitline pair, i.e., every set of memory cell rows. Accordingly, two writerow selection gates WRSG corresponding to the same set are turned ON/OFFin response to the common write row selection line WRSL.

[0513] For example, the write row selection gates WRSG1 and WRSG2corresponding to the first and second memory cell rows operate inresponse to the common write row selection line WRSL1.

[0514] The write row selection gates WRSG1, WRSG3, . . . correspondingto the write bit lines WBL of the odd rows are each electrically coupledbetween the corresponding write bit line WBL and the write data lineWDL. The write row selection gates WRSG2, WRSG4, . . . corresponding tothe write bit lines /WBL of the even rows are each electrically coupledbetween the corresponding write bit line /WBL and the write data line/WDL.

[0515] In response to the write row selection line WRSL activatedaccording to the row selection result, corresponding two write rowselection gates WRSG are turned ON. As a result, the write bit lines WBLand /WBL of the write bit line pair corresponding to the selected memorycell row are electrically coupled to the write data lines WDL and /WDLof the write data line pair, respectively.

[0516] Moreover, the equalizing transistors 62 for connecting the writebit lines WBL and /WBL of the respective write bit line pair to eachother are provided instead of the bit line current control transistors63 shown in FIG. 35. The equalizing transistor 62 operates in responseto, e.g., the control signal WE so as to short-circuit two write bitlines forming the same write bit line pair in the data write operation.The same write bit line voltage control transistors 65 as thosedescribed in connection with FIG. 35 are provided corresponding to therespective write bit lines WBL and /WBL.

[0517] The data write current ±Iw is supplied from the data writecircuit 51 b to the write data lines WDL and /WDL of the write data linepair in the same manner as that of the write data buses WDB and /WDB ofthe first embodiment. Since the structure and operation of the datawrite circuit 51 b have been described in connection with FIG. 7,detailed description thereof will not be repeated.

[0518] As a result, the data write operation can be conducted in thewrite bit line pair corresponding to the row selection result, by usinga reciprocating current returned at the equalizing transistor 62.

[0519] With such a structure, in the data read operation, a selectedread bit line pair is supplied with the sense current in the same manneras that of the bit line pair of the first embodiment. Similarly, in thedata write operation, a selected write bit line pair is supplied withthe data write current thorough the corresponding equalizing transistor62 in the same manner as that of the bit line pair of the firstembodiment.

[0520] Therefore, in the case where the memory cells according to thefifth embodiment capable of reducing the chip area are arranged in rowsand columns, the read and write operation margins can be ensured usingthe folded bit line structure.

[0521] Fourth Modification of Fifth Embodiment

[0522] In the fourth modification of the fifth embodiment, the write bitline WBL is shared between adjacent memory cells, in addition to thefolded bit line structure shown in the third modification of the fifthembodiment.

[0523] Referring to FIG. 40, in the memory array according to the fourthmodification of the fifth embodiment, adjacent memory cells in thecolumn direction share the same write bit line WBL.

[0524] In the read operation, the read word line RWL is activated. Ineach read bit line RBL, the memory cells are provided every other readword line RWL. Moreover, the memory cells are arranged alternatelybetween every adjacent read bit lines RBL. Therefore, every set ofadjacent two memory cell columns form a read bit line pair, so that thedata read operation can be conducted based on the folded bit linestructure in the same manner as that of the third modification of thefifth embodiment.

[0525] On the other hand, the data write operation cannot be conductedbased on the folded bit line structure because the write bit line WBL isshared. Accordingly, in the fourth modification of the fifth embodiment,the peripheral circuitry associated with selection of the write bit lineWBL is arranged in the same manner as that shown in FIG. 35. Thus, as inthe case of the fifth embodiment, the data write operation can beconducted using the data write circuit 51 b having a simple structure.

[0526] Although the data write operation cannot be conducted based onthe folded bit line structure, the pitch of the write bit lines WBL inthe memory array 10 can be widened. As a result, further improvedintegration of the memory array 10 and thus further reduced chip area ofthe MRAM device can be achieved. Improved reliability of the MRAM devicecan also be achieved by increasing the electromigration resistance ofthe write bit lines WWL.

[0527] Note that, although FIG. 40 shows the structure in which thewrite bit line WBL out of the signal wirings associated with the datawrite operation is shared between adjacent memory cells, it is alsopossible to share the write word line WWL instead of the write bit lineWBL. In this case, however, the write bit line WBL cannot be shared, andmust be provided in every memory cell row. Which of the wirings shouldbe shared to widen the wiring pitch can be determined in view of thestructural conditions, design and the like, such as the distance fromthe magnetic tunnel junction MTJ.

[0528] Fifth Modification of Fifth Embodiment

[0529] In the fifth modification of the fifth embodiment, the read wordline RWL is shared between adjacent memory cells, in addition to thefolded bit line structure of the third modification of the fifthembodiment.

[0530] Referring to FIG. 41, in the memory array according to the fifthmodification of the fifth embodiment, adjacent memory cells in thecolumn direction share the same read word line RWL.

[0531] The read/write control circuit 60 includes the equalizingtransistors 62, precharging transistors 64 and write bit line voltagecontrol transistors 65, which are arranged in the same manner as that ofthe third modification of the fifth embodiment.

[0532] In the data write operation, the write word line WWL isactivated. In each write bit line WBL, the memory cells are providedevery other write word line WWL. Moreover, the memory cell are arrangedalternately between every adjacent write bit lines WBL. Therefore, everyset of adjacent two memory cell rows can form a write bit line pair. Asa result, the data write opera ion can be conducted based on the foldedbit line structure in the same manner as that of the third modificationof the fifth embodiment, so that the same effects can be obtained.

[0533] On the other hand, in the data read operation, the read word lineRWL shared by a plurality of memory cell rows is activated. Therefore,the data read operation cannot be conducted based on the folded bit linestructure. Accordingly, in the fifth modification of the fifthembodiment, the peripheral circuitry associated with selection of theread bit line RBL is arranged in the same manner as that shown in FIG.35.

[0534] With such a structure, the read operation margin based on thefolded bit line structure cannot be ensured, but the pitch of the readword lines RWL in the memory array 10 can be widened, and the data readoperation can be conducted normally. As a result, improved integrationof the memory array 10 and thus reduced chip area of the MRAM device canbe achieved.

[0535] Accordingly, by conducting the data write operation based on thefolded bit line structure using the memory cells of the fifthembodiment, the write operation margin can be ensured as well as asimplified structure of the peripheral circuitry and reduced data writenoise can be achieved. Moreover, by sharing the read word line RWL,improved integration of the memory array 10 can also be achievedsimultaneously.

[0536] Note that, although FIG. 41 shows the structure in which the readword line RWL out of the signal wirings associated with the data readoperation is shared between adjacent memory cells, it is also possibleto share the read bit line RBL instead of the read word line RWL. Inthis case, however, the read word line RWL cannot be shared, and must beprovided in every memory cell row. Which of the wirings should be sharedto widen the wiring pitch can be determined as appropriate in view ofthe structural conditions, design and the like.

[0537] Sixth Embodiment

[0538] Referring to FIG. 42, the MTJ memory cell according to the sixthembodiment is different from that shown in FIG. 32 in connection betweenthe read bit line RBL and the write bit line WBL. More specifically, theread bit line RBL is not directly coupled to the magnetic tunneljunction MTJ, but coupled thereto in response to turning-ON of theaccess transistor ATR. Moreover, the write bit line WBL is coupled tothe magnetic tunnel junction MTJ so as to be included in the sensecurrent path in the data read operation.

[0539] Including the extending direction of each signal wiring, thestructure is otherwise the same as that of FIG. 32. Therefore, detaileddescription thereof will not be repeated. Moreover, the voltage andcurrent waveforms of each wiring in the data read and write operationsare also the same as those of FIG. 33. Therefore, detailed descriptionthereof will not be repeated.

[0540] Accordingly, the write word line WWL is provided near themagnetic tunnel junction MTJ so as to extend perpendicularly to thewrite bit line WBL. As a result, the read word line driver 30 r and thewrite word line driver 30 w can be independently provided, whereby thesame effects as those of the fifth embodiment can be obtained.

[0541] Moreover, the write word line WWL can be independently providedwithout being coupled to other portions of the MTJ memory cell.Therefore, the write word line WWL can be arbitrarily arranged so as toimprove the magnetic coupling with the magnetic tunnel junction MTJ.

[0542] Moreover, the read bit line RBL is coupled to the magnetic tunneljunction MTJ through the access transistor ATR. Therefore, the number ofmagnetic tunnel junctions MTJ coupled to the read bit lines RBL isreduced, and the capacitance of the read bit line RBL is reduced. As aresult, the data read speed can be increased.

[0543] Referring to FIG. 43, in the MTJ memory cell according to thesixth embodiment, the read bit line RBL is provided in the first metalwiring layer M1 so as to be electrically coupled to the source/drainregion 110 of the access transistor ATR. The read word line RWL isprovided in the same layer as that of the gate 130 of the accesstransistor ATR. The source/drain region 120 of the access transistor ATRis coupled to the magnetic tunnel junction MTJ through the metal wiringsprovided in the first and second metal wiring layers M1 and M2, thebarrier metal 140, and the metal film 150 provided in the contact hole.

[0544] The magnetic tunnel junction MTJ is provided between the secondand third metal wiring layers M2 and M3. The write bit line WBL isprovided in the third metal wiring layer M3 so as to be electricallycoupled to the magnetic tunnel junction MTJ. The write word line WWL isprovided in the second metal wiring layer M2. At this time, the writeword line WWL is provided so as to enable improved magnetic couplingwith the magnetic tunnel junction MTJ.

[0545] In the MTJ memory cell according to the sixth embodiment, thedistance between the write bit line WBL and the magnetic tunnel junctionMTJ can be reduced as compared to that in the MTJ memory cell of thefifth embodiment shown in FIG. 34. Accordingly, the amount of data writecurrent flowing through the write bit line WBL can be reduced.

[0546] The write word line WWL is located farther from the magnetictunnel junction MTJ than is the write bit line WBL. Therefore, in theMTJ memory cell of the sixth embodiment, a relatively large data writecurrent must be applied to the write word line WWL.

[0547] Referring to FIG. 44, in the memory array according to the sixthembodiment, the memory cells MC having the structure of FIG. 42 arearranged in rows and columns. The read word lines RWL and the write wordlines WWL extend in the row and column directions, respectively. Theread bit lines RBL and the write bit lines WBL extend in the column androw directions, respectively.

[0548] Adjacent memory cells in the row direction share the read bitline RBL, and adjacent memory cells in the column direction share thewrite bit line WBL.

[0549] For example, the memory cell group of the first and second memorycell columns shares the same read bit line RBL1, and the memory cellgroup of the third and fourth memory cell columns shares the same readbit line RBL2. Moreover, the memory cell group of the second and thirdmemory cell rows shares the write bit line WBL2. In the following memorycell rows and columns as well, the read bit lines RBL and the write bitlines WBL are arranged similarly.

[0550] If the data is to be read from or written to a plurality ofmemory cells MC of the same read bit line RBL or write bit line WBL,data collision occurs. Accordingly, the memory cells MC are arrangedalternately.

[0551] With such a structure, the pitches of the read bit lines RBL andthe write bit lines WBL in the memory array 10 can be widened as in thecase of the fifth embodiment. As a result, the memory cells MC can beefficiently arranged, whereby improved integration of the memory array10 as well as reduced chip area of the MRAM device can be achieved.

[0552] Since the structure of the peripheral circuitry for selectivelysupplying the data write current and the sense current to the read bitline RBL and the write bit line WBL is the same as that of FIG. 35,detailed description thereof will not be repeated.

[0553] First Modification of Sixth Embodiment

[0554] Referring to FIG. 45, in the memory array according to the firstmodification of the sixth embodiment, adjacent memory cells share thesame write word line WWL. For example, the memory cell group of thesecond and third memory cell columns shares a single write word lineWWL2. In the following memory cell columns as well, the write word linesWWL are arranged similarly.

[0555] In order to conduct the data write operation normally, aplurality of memory cells MC must not be present at the intersection ofthe same write word line WWL and the same write bit line WBL.Accordingly, the memory cells MC are arranged alternately.

[0556] Moreover, like the sixth embodiment, adjacent memory cells in therow direction share the read bit line RBL.

[0557] Since the structure of the peripheral circuitry associated withthe data read and write operations through the read bit line RBL andwrite bit line WBL, as well as the memory cell operation in reading andwriting the data are the same as those of the sixth embodiment, detaileddescription thereof will not be repeated.

[0558] As described before, in the MTJ memory cell of the sixthembodiment, a relatively large data write current must be applied to thewrite word line WWL. Accordingly, the write word line WWL is sharedbetween adjacent memory cells so as to ensure the line pitch thereof. Asa result, the line width, i.e., the cross-sectional area, of the writeword line WWL is assured, so that the current density thereof can besuppressed. As a result, improved reliability of the MRAM device can beachieved. As described before, for the improved operation reliability,it is also effective to select a material of these wirings in view ofelectromigration resistance.

[0559] Second Modification of Sixth Embodiment

[0560] Referring to FIG. 46, in the memory array according to the secondmodification of the sixth embodiment, adjacent memory cells in thecolumn direction also share the same read word line RWL. For example,the memory cell group of the second and third memory cell rows sharesthe same read word line RWL2. In the following memory cell rows as well,the read word lines RWL are arranged similarly.

[0561] In order to conduct the data read operation normally, a pluralityof memory cells MC selected by the same read word line RWL must not besimultaneously coupled to the same read bit line RBL. Accordingly, theread bit line RBL is provided in every memory cell column, and thememory cells MC are arranged alternately.

[0562] With such a structure, the pitch of the write word lines WWL inthe memory array 10 can be widened. As a result, the memory cells MC canbe efficiently arranged, whereby improved integration of the memoryarray 10 as well as reduced chip area of the MRAM device can beachieved.

[0563] Third Modification of Sixth Embodiment

[0564] Referring to FIG. 47, for the memory cells having the structureof the sixth embodiment and arranged in rows and columns, the folded bitline structure is realized in every set of adjacent two memory cellcolumns, using corresponding two read bit lines RBL. For example, a readbit line pair can be formed from the read bit lines RBL1 and RBL2(/RBL1) respectively corresponding to the first and second memory cellcolumns.

[0565] Similarly, the folded bit line structure is realized in every setof adjacent two memory cell rows, using corresponding two write bitlines WBL. For example, a write bit line pair can be formed from thewrite bit lines WBL1 and WBL2 (/WBL1) respectively corresponding to thefirst and second memory cell rows.

[0566] The structure of the peripheral circuitry for conducting rowselection from the write bit lines WBL and /WBL of the write bit linepairs and supplying the data write current ±Iw thereto, and forconducting column selection from the read bit lines RBL and /RBL of theread bit line pairs and supplying the sense current Is thereto is thesame as that shown in FIG. 39. Therefore, detailed description thereofwill not be repeated.

[0567] Accordingly, even when the memory cells according to the sixthembodiment are arranged in rows and columns, the read and writeoperation margins can be ensured using the folded bit line structure.

[0568] Fourth Modification of Sixth Embodiment

[0569] In the fourth modification of the sixth embodiment, the write bitline WBL is shared between adjacent memory cells, in addition to thefolded bit line structure shown in the third modification of the sixthembodiment.

[0570] Referring to FIG. 48, in the memory array according to the fourthmodification of the sixth embodiment, adjacent memory cells in thecolumn direction share the same write bit line WBL.

[0571] In the read operation, the read word line RWL is activated. Ineach read bit line RBL, the memory cells are provided every other readword line RWL. Moreover, the memory cells are arranged alternatelybetween every adjacent read bit lines RBL. Therefore, every set ofadjacent two memory cell columns form a read bit line pair, so that thedata read operation can be conducted based on the folded bit linestructure in the same manner as that of the third modification of thesixth embodiment.

[0572] On the other hand, the data write operation cannot be conductedbased on the folded bit line structure because the write bit line WBL isshared. Accordingly, in the fourth modification of the sixth embodiment,the peripheral circuitry associated with selection of the write bit lineWBL is arranged in the same manner as that shown in FIG. 44. Thus, as inthe case of the sixth embodiment, the data write operation can beconducted using the data write circuit 51 b having a simple structure.

[0573] Although the data write operation cannot be conducted based onthe folded bit line structure, the pitch of the write bit lines WBL inthe memory array 10 can be widened. As a result, further improvedintegration of the memory array 10 and thus further reduced chip area ofthe MRAM device can be achieved.

[0574] Note that, although FIG. 48 shows the structure in which thewrite bit line WBL out of the signal wirings associated with the datawrite operation is shared between adjacent memory cells, it is alsopossible to share the write word line WWL instead of the write bit lineWBL. In this case, however, the write bit line WBL cannot be shared, andmust be provided in every memory cell row. Which of the wirings shouldbe shared to widen the wiring pitch can be determined in view of thedistance from the magnetic tunnel junction MTJ, and the like.

[0575] Fifth Modification of Sixth Embodiment

[0576] In the fifth modification of the sixth embodiment, the read wordline RWL is shared between adjacent memory cells, in addition to thefolded bit line structure of the third modification of the sixthembodiment.

[0577] Referring to FIG. 49, in the memory array according to the fifthmodification of the sixth embodiment, adjacent memory cells in thecolumn direction share the same read word line RWL.

[0578] The read/write control circuit 60 includes the equalizingtransistors 62, precharging transistors 64 and write bit line voltagecontrol transistors 65, which are arranged in the same manner as that ofthe third modification of the sixth embodiment.

[0579] In the data write operation, the write word line WWL isactivated. In each write bit line WBL, the memory cells are providedevery other write word line WWL. Moreover, the memory cells are arrangedalternately between every adjacent write bit lines WBL. Therefore, everyset of adjacent two memory cell rows can form a write bit line pair. Asa result, the data write operation can be conducted based on the foldedbit line structure in the same manner as that of the third modificationof the fifth embodiment, so that the same effects can be obtained.

[0580] On the other hand, in the data read operation, the read word lineRWL shared by a plurality of memory cell rows is activated. Therefore,the data read operation cannot be conducted based on the folded bit linestructure. Accordingly, in the fifth modification of the sixthembodiment, the peripheral circuitry associated with selection of theread bit line RBL is arranged in the same manner as that shown in FIG.44.

[0581] With such a structure, the read operation margin based on thefolded bit line structure cannot be ensured, but the pitch of the readword lines RWL in the memory array 10 can be widened, and the data readoperation can be conducted normally. As a result, improved integrationof the memory array 10 and thus reduced chip area of the MRAM device canbe achieved.

[0582] Accordingly, by conducting the data write operation based on thefolded bit line structure using the memory cells of the sixthembodiment, the write operation margin can be ensured as well as asimplified structure of the peripheral circuitry and reduced data writenoise can be achieved. Moreover, by sharing the read word line RWL,improved integration of the memory array 10 can also be achievedsimultaneously.

[0583] Note that, although FIG. 49 shows the structure in which the readword line RWL out of the signal wirings associated with the data readoperation is shared between adjacent memory cells, it is also possibleto share the read bit line RBL instead of the read word line RWL. Inthis case, however, the read word line RWL cannot be shared, and must beprovided in every memory cell row. Which of the wirings should be sharedto widen the wiring pitch can be determined as appropriate in view ofthe structural conditions, design and the like.

[0584] Seventh Embodiment

[0585] Referring to FIG. 50, in the MTJ memory cell according to theseventh embodiment, the read bit line RBL is coupled to the magnetictunnel junction MTJ through the access transistor ATR. The magnetictunnel junction MTJ is coupled between the write word line WWL and theaccess transistor ATR. The read word line RWL is coupled to the gate ofthe access transistor ATR. In the structure of FIG. 50 as well, the readword line RWL and the write word line WWL extend perpendicularly to eachother.

[0586] Referring to FIG. 51, the read bit line RBL is provided in themetal wiring layer M1. The read word line RWL is formed in the samelayer as that of the gate 130 of the access transistor ATR. The read bitline RBL is coupled to the source/drain region 110 of the accesstransistor ATR. The source/drain region 120 is coupled to the magnetictunnel junction MTJ through the metal wirings provided in the first andsecond metal wiring layers M1 and M2, the barrier metal 140, and themetal film 150 provided in the contact hole.

[0587] The write bit line WBL is provided in the second metal wiringlayer M2 near the magnetic tunnel junction MTJ. The write word line WWLis provided in the third metal wiring layer M3 so as to be electricallycoupled to the magnetic tunnel junction MTJ.

[0588] With such a structure, the read bit line RBL is coupled to themagnetic tunnel junction MTJ through the access transistor ATR.Accordingly, the read bit line RBL is electrically coupled only to theMTJ memory cell MC to be read, i.e., the MTJ memory cell MC of thememory cell row corresponding to the read word line RWL activated to theselected state (H level). Accordingly, the capacitance of the read bitline RBL can be suppressed, whereby a high-speed data read operation canbe achieved.

[0589] Note that, in the MTJ memory cell of the seventh embodiment, thevoltage and current waveforms of each wiring in the data read and writeoperations are the same as those of FIG. 33. Therefore, detaileddescription thereof will not be repeated.

[0590] In the MTJ memory cell according to the seventh embodiment aswell, the distance between the write bit line WBL and the magnetictunnel junction MTJ can be reduced as compared to that in the MTJ memorycell of the fifth embodiment shown in FIG. 34. Accordingly, the amountof data write current flowing through the write bit line WBL can bereduced.

[0591] The write bit line WBL is located farther from the magnetictunnel junction MTJ than is the write word line WWL. Therefore, in theMTJ memory cell of the seventh embodiment, a relatively large data writecurrent must be applied to the write bit line WBL.

[0592] Referring to FIG. 52, in the memory array according to theseventh embodiment, the memory cells MC shown in FIG. 50 are arranged inrows and columns. The read word lines RWL and the write word lines WWLextend in the row and column directions, respectively. The read bitlines RBL and the write bit lines WBL extend in the column and rowdirections, respectively.

[0593] Adjacent memory cells in the row direction share the read bitline RBL, and adjacent memory cells in the column direction share thewrite bit line WBL.

[0594] For example, the memory cell group of the first and second memorycell columns shares the same read bit line RBL1, and the memory cellgroup of the third and fourth memory cell columns shares the same readbit line RBL2. Moreover, the memory cell group of the second and thirdmemory cell rows shares the write bit line WBL2. In the following memorycell rows and columns as well, the read bit lines RBL and the write bitlines WBL are arranged similarly.

[0595] If the data is to be read from or written to a plurality ofmemory cells MC of the same read bit line RBL or write bit line WBL,data collision occurs. Accordingly, the memory cells MC are arrangedalternately.

[0596] With such a structure, the pitches of the read bit lines RBL andthe write bit lines WBL in the memory array 10 can be widened. As aresult, the memory cells MC can be efficiently arranged, wherebyimproved integration of the memory array 10 as well as reduced chip areaof the MRAM device can be achieved.

[0597] Since the structure of the peripheral circuitry for selectivelysupplying the data write current and the sense current to the read bitline RBL and the write bit line WBL is the same as that of FIG. 35,detailed description thereof will not be repeated.

[0598] As described before, in the MTJ memory cell of the seventhembodiment, a relatively large data write current must be applied to thewrite bit line WBL. Accordingly, the write bit line WBL is sharedbetween adjacent memory cells so as to ensure the line pitch thereof. Asa result, the line width, i.e., the cross-sectional area, of the writebit line WBL is assured, so that the current density thereof can besuppressed. As a result, improved reliability of the MRAM device can beachieved. As described before, for the improved operation reliability,it is also effective to select a material of these wirings in view ofelectromigration resistance.

[0599] First Modification of Seventh Embodiment

[0600] Referring to FIG. 53, in the memory array according to the firstmodification of the seventh embodiment, adjacent memory cells share thesame write word line WWL. For example, the memory cell group of thesecond and third memory cell columns shares a single write word lineWWL2. In the following memory cell columns as well, the write word linesWWL are arranged similarly.

[0601] In order to conduct the data write operation normally, aplurality of memory cells MC must not be present at the intersection ofthe same write word line WWL and the same write bit line WBL.Accordingly, the memory cells MC are arranged alternately.

[0602] Moreover, like the seventh embodiment, adjacent memory cells inthe row direction share the read bit line RBL.

[0603] Since the structure of the peripheral circuitry associated withthe data read and write operations through the read bit line RBL andwrite bit line WBL, as well as the memory cell operation in reading andwriting the data are the same as those of the seventh embodiment,detailed description thereof will not be repeated.

[0604] With such a structure, the pitches of the read bit lines RBL andthe write word lines WWL in the memory array 10 can be widened. As aresult, the memory cells MC can be efficiently arranged, wherebyimproved integration of the memory array 10 as well as reduced chip areaof the MRAM device can be achieved.

[0605] Second Modification of Seventh Embodiment

[0606] Referring to FIG. 54, in the memory array according to the secondmodification of the seventh embodiment, adjacent memory cells in thecolumn direction share the same read word line RWL. For example, thememory cell group of the second and third memory cell rows shares thesame read word line RWL2. In the following memory cell rows as well, theread word lines RWL are arranged similarly.

[0607] Moreover, adjacent memory cells in the row direction share thesame write word line WWL. For example, the memory cell group of thesecond and third memory cell columns shares the same write word lineWWL2. In the following memory cell columns as well, the write word linesWWL are arranged similarly.

[0608] In order to conduct the data read and write operations normally,a plurality of memory cells MC selected by the same read word line RWLor write word line WWL must not be simultaneously coupled to the sameread bit line RBL or write bit line WBL. Accordingly, the read bit lineRBL and the write bit line WBL are provided in every memory cell columnand every memory cell row, respectively, and the memory cells MC arearranged alternately.

[0609] Since the structure is otherwise the same as that of the seventhembodiment, detailed description thereof will not be repeated.

[0610] With such a structure, the pitches of the write word lines WWLand read word lines RWL in the memory array 10 can be widened. As aresult, the memory cells MC can be more efficiently arranged, wherebyimproved integration of the memory array 10 as well as reduced chip areaof the MRAM device can be achieved.

[0611] Third Modification of Seventh Embodiment

[0612] Referring to FIG. 55, for the memory cells having the structureof the seventh embodiment and arranged in rows and columns, the foldedbit line structure is realized in every set of adjacent two memory cellcolumns, using corresponding two read bit lines RBL. For example, a readbit line pair can be formed from the read bit lines RBL1 and RBL2(/RBL1) respectively corresponding to the first and second memory cellcolumns.

[0613] Similarly, the folded bit line structure is realized in every setof adjacent two memory cell rows, using corresponding two write bitlines WBL. For example, a write bit line pair can be formed from thewrite bit lines WBL1 and WBL2 (/WBL1) respectively corresponding to thefirst and second memory cell rows.

[0614] The structure of the peripheral circuitry for conducting rowselection from the write bit lines WBL and /WBL of the write bit linepairs and supplying the data write current ±Iw thereto, and forconducting column selection from the read bit lines RBL and /RBL of theread bit line pairs and supplying the sense current Is thereto is thesame as that shown in FIG. 39. Therefore, detailed description thereofwill not be repeated.

[0615] Accordingly, even when the memory cells according to the seventhembodiment are arranged in rows and columns, the read and writeoperation margins can be ensured using the folded bit line structure.

[0616] Fourth Modification of Seventh Embodiment In the fourthmodification of the seventh embodiment, the write word line WWL isshared between adjacent memory cells, in addition to the folded bit linestructure shown in the third modification of the seventh embodiment.

[0617] Referring to FIG. 56, in the memory array according to the fourthmodification of the seventh embodiment, adjacent memory cells in the rowdirection share the same write word line WWL.

[0618] In the read operation, the read word line RWL is activated. Ineach read bit line RBL, the memory cells are provided every other readword line RWL. Moreover, the memory cells are arranged alternatelybetween every adjacent read bit lines RBL. Therefore, every set ofadjacent two memory cell columns form a read bit line pair, so that thedata read operation can be conducted based on the folded bit linestructure in the same manner as that of the third modification of theseventh embodiment.

[0619] On the other hand, the data write operation cannot be conductedbased on the folded bit line structure because the write word line WWLis shared. Accordingly, in the fourth modification of the seventhembodiment, the peripheral circuitry associated with selection of thewrite bit line WBL is arranged in the same manner as that shown in FIG.52. Thus, as in the case of the seventh embodiment, the data writeoperation can be conducted using the data write circuit 51 b having asimple structure.

[0620] Although the data write operation cannot be conducted based onthe folded bit line structure, the pitch of the write word lines WWL inthe memory array 10 can be widened. As a result, further improvedintegration of the memory array 10 and thus further reduced chip area ofthe MRAM device can be achieved.

[0621] Note that, although FIG. 56 shows the structure in which thewrite word line WWL out of the signal wirings associated with the datawrite operation is shared between adjacent memory cells, it is alsopossible to share the write bit line WBL instead of the write word lineWWL. In this case, however, the write word line WWL cannot be shared,and must be provided in every memory cell column. Which of the wiringsshould be shared to widen the wiring pitch can be determined in view ofthe distance from the magnetic tunnel junction MTJ, and the like.

[0622] Fifth Modification of Seventh Embodiment

[0623] In the fifth modification of the seventh embodiment, the readword line RWL is shared between adjacent memory cells, in addition tothe folded bit line structure of the third modification of the seventhembodiment.

[0624] Referring to FIG. 57, in the memory array according to the fifthmodification of the seventh embodiment, adjacent memory cells in thecolumn direction share the same read word line RWL.

[0625] The read/write control circuit 60 includes the equalizingtransistors 62, precharging transistors 64 and write bit line voltagecontrol transistors 65, which are arranged in the same manner as that ofthe third modification of the seventh embodiment.

[0626] In the data write operation, the write word line WWL isactivated. In each write bit line WBL, the memory cells are providedevery other write word line WWL. Moreover, the memory cells are arrangedalternately between every adjacent write bit lines WBL. Therefore, everyset of adjacent two memory cell rows can form a write bit line pair. Asa result, the data write operation can be conducted based on the foldedbit line structure in the same manner as that of the third modificationof the fifth embodiment, so that the same effects can be obtained.

[0627] On the other hand, in the data read operation, the read word lineRWL shared by a plurality of memory cell rows is activated. Therefore,the data read operation cannot be conducted based on the folded bit linestructure. Accordingly, in the fifth modification of the seventhembodiment, the peripheral circuitry associated with selection of theread bit line RBL is arranged in the same manner as that shown in FIG.52.

[0628] With such a structure, the read operation margin based on thefolded bit line structure cannot be ensured, but the pitch of the readword lines RWL in the memory array 10 can be widened, and the data readoperation can be conducted normally. As a result, improved integrationof the memory array 10 and thus reduced chip area of the MRAM device canbe achieved.

[0629] Accordingly, by conducting the data write operation based on thefolded bit line structure using the memory cells of the seventhembodiment, the write operation margin can be ensured as well as asimplified structure of the peripheral circuitry and reduced data writenoise can be achieved. Moreover, by sharing the read word line RWL,improved integration of the memory array 10 can also be achievedsimultaneously.

[0630] Note that, although FIG. 57 shows the structure in which the readword line RWL out of the signal wirings associated with the data readoperation is shared between adjacent memory cells, it is also possibleto share the read bit line RBL instead of the read word line RWL. Inthis case, however, the read word line RWL cannot be shared, and must beprovided in every memory cell row. Which of the wirings should be sharedto widen the wiring pitch can be determined as appropriate in view ofthe structural conditions, design and the like.

[0631] Eighth Embodiment

[0632] Referring to FIG. 58, the MTJ memory cell according to the eighthmodification is different from that of the seventh embodiment shown inFIG. 50 in that the read bit line RBL and the write word line WWL areswitched in position. Since the arrangement of the lines is otherwisethe same as that of FIG. 50, description thereof will not be repeated.Such a structure also allows the read word line RWL and the write wordline WWL to extend perpendicularly to each other.

[0633] Referring to FIG. 59, the structure of the MTJ memory cellaccording to the eighth embodiment is different from that of the seventhembodiment shown in FIG. 51 in that the write word line WWL and the readbit line RBL are switched in position. More specifically, the write wordline WWL is provided in the first metal wiring layer M1 so as to becoupled to the source/drain region 110 of the access transistor ATR. Theread bit line RBL is provided in the third metal wiring layer M3 so asto be electrically coupled to the magnetic tunnel junction MTJ.

[0634] In the eighth embodiment, the read bit line RBL is directlycoupled to the magnetic tunnel junction MTJ. Therefore, such anincreased read operation speed as in the seventh embodiment cannot beachieved. However, in the structure of the eighth embodiment as well,the read word line driver 30 r and the write word line driver 30 w canbe independently provided, whereby the same effects as those of theseventh embodiment can be obtained.

[0635] Note that, in the MTJ memory cell of the eighth embodiment, thevoltage and current waveforms of each wiring in the data read and writeoperations are the same as those of FIG. 33. Therefore, detaileddescription thereof will not be repeated.

[0636] In the MTJ memory cell according to the eighth embodiment, thewrite word line WWL is located farther from the magnetic tunnel junctionMTJ than is the write bit line WBL. Therefore, a relatively large datawrite current must be applied to the write word line WWL.

[0637] Referring to FIG. 60, in the memory array according to the eighthembodiment, the memory cells MC having the structure shown in FIG. 58are arranged in rows and columns. The read word lines RWL and the writeword lines WWL extend in the row and column directions, respectively.The read bit lines RBL and the write bit lines WBL extend in the columnand row directions, respectively.

[0638] Adjacent memory cells in the row direction share the same writeword line WWL.

[0639] For example, the memory cell group of the first and second memorycell columns shares the same write word line WWL1, and the memory cellgroup of the third and fourth memory cell columns shares the same writeword line WWL2. In the following memory cell columns as well, the writeword lines WWL are arranged similarly.

[0640] If the data is to be written to a plurality of memory cells MC ofthe same write bit line WBL, data collision occurs. Accordingly, thememory cells MC are arranged alternately.

[0641] With such a structure, the pitch of the write word lines WWL inthe memory array 10 can be widened. As a result, the memory cells MC canbe efficiently arranged, whereby improved integration of the memoryarray 10 as well as reduced chip area of the MRAM device can beachieved.

[0642] Since the structure of the peripheral circuitry for selectivelysupplying the data write current and the sense current to the read bitline RBL and the write bit line WBL is the same as that of FIG. 35,detailed description thereof will not be repeated.

[0643] As described before, in the MTJ memory cell of the eighthembodiment, a relatively large data write current must be applied to thewrite word line WWL. Accordingly, the write word line WWL is sharedbetween adjacent memory cells so as to ensure the line pitch thereof. Asa result, the line width, i.e., the cross-sectional area, of the writeword line WWL is assured, so that the current density thereof can besuppressed. Thus, improved reliability of the MRAM device can beachieved. As described before, for the improved operation reliability,it is also effective to select a material of these wirings in view ofelectromigration resistance.

[0644] First Modification of Eighth Embodiment

[0645] Referring to FIG. 61, in the memory array according to the firstmodification of the eighth embodiment, adjacent memory cells share thesame read bit line RBL. For example, the memory cell group of the secondand third memory cell columns shares the same read bit line RBL2. In thefollowing memory cell columns as well, the read bit lines RBL arearranged similarly.

[0646] In order to conduct the data read operation normally, a pluralityof memory cells MC must not be present at the intersection of the sameread word line RWL and the same read bit line RBL. Accordingly, thememory cells MC are arranged alternately.

[0647] Moreover, adjacent memory cells share the same write bit lineWBL. For example the memory cell group of the first and second memorycell rows shares the same write bit line WBL1. In the following memorycell rows as well, the write bit lines WBL are arranged similarly.

[0648] In order to conduct the data write operation normally, aplurality of memory cells MC must not be present at the intersection ofthe same write word line WWL and the same write bit line WBL.

[0649] Since the structure of the peripheral circuitry associated withthe data read and write operations through the read bit line RBL andwrite bit line WBL, as well as the memory cell operation in reading andwriting the data are the same as those of the eighth embodiment,detailed description thereof will not be repeated.

[0650] With such a structure, the pitches of the read bit lines RBL andthe write bit lines WBL in the memory array 10 can be widened. As aresult, the memory cells MC can be efficiently arranged, wherebyimproved integration of the memory array 10 as well as reduced chip areaof the MRAM device can be achieved.

[0651] Second Modification of Eighth Embodiment

[0652] Referring to FIG. 62, in the memory array according to the secondmodification of the eighth embodiment, adjacent memory cells in thecolumn direction share the same read word line RWL. For example, thememory cell group of the second and third memory cell rows shares thesame read word line RWL2. In the following memory cell rows as well, theread word lines RWL are arranged similarly.

[0653] Moreover, adjacent memory cells in the column direction share thesame write bit line WBL. For example, the memory cell group of the firstand second memory cell rows shares the same write bit line WBL1. In thefollowing memory cell rows as well, the write bit lines WBL are arrangedsimilarly.

[0654] In order to conduct the data read operation normally, a pluralityof memory cells MC selected by the same read word line RWL must not besimultaneously coupled to the same read bit line RBL. Accordingly, theread bit line RBL is provided in every memory cell column, and thememory cells MC are arranged alternately.

[0655] Since the structure is otherwise the same as that of the eighthembodiment, detailed description thereof will not be repeated.

[0656] With such a structure, the pitch of the read word lines RWL inthe memory array 10 can be widened. As a result, the memory cells MC canbe efficiently arranged, whereby improved integration of the memoryarray 10 as well as reduced chip area of the MRAM device can beachieved.

[0657] Third Modification of Eighth Embodiment

[0658] Referring to FIG. 63, for the memory cells having the structureof the eighth embodiment and arranged in rows and columns, the foldedbit line structure is realized in every set of adjacent two memory cellcolumns, using corresponding two read bit lines RBL. For example, a readbit line pair can be formed from the read bit lines RBL1 and RBL2(/RBL1) respectively corresponding to the first and second memory cellcolumns.

[0659] Similarly, the folded bit line structure is realized in every setof adjacent two memory cell rows, using corresponding two write bitlines WBL. For example, a write bit line pair can be formed from thewrite bit lines WBL1 and WBL2 (/WBL1) respectively corresponding to thefirst and second memory cell rows.

[0660] The structure of the peripheral circuitry for conducting rowselection from the write bit lines WBL and /WBL of the write bit linepairs and supplying the data write current +Iw thereto, and forconducting column selection from the read bit lines RBL and /RBL of theread bit line pairs and supplying the sense current Is thereto is thesame as that shown in FIG. 39. Therefore, detailed description thereofwill not be repeated.

[0661] Accordingly, even when the memory cells according to the eighthembodiment are arranged in rows and columns, the data read and writeoperation margins can be ensured using the folded bit line structure.

[0662] Fourth Modification of Eighth Embodiment

[0663] In the fourth modification of the eighth embodiment, the writeword line WWL is shared between adjacent memory cells, in addition tothe folded bit line structure shown in the third modification of theeighth embodiment.

[0664] Referring to FIG. 64, in the memory array according to the fourthmodification of the eighth embodiment, adjacent memory cells in the rowdirection share the same write word line WWL.

[0665] In the read operation, the read word line RWL is activated. Ineach read bit line RBL, the memory cells are provided every other readword line RWL. Moreover, the memory cells are arranged alternatelybetween every adjacent read bit lines RBL. Therefore, every set ofadjacent two memory cell columns form a read bit line pair, so that thedata read operation can be conducted based on the folded bit linestructure in the same manner as that of the third modification of theeighth embodiment.

[0666] On the other hand, the data write operation cannot be conductedbased on the folded bit line structure because the write word line WWLis shared. Accordingly, in the fourth modification of the eighthembodiment, the peripheral circuitry associated with selection of thewrite bit line WBL is arranged in the same manner as that shown in FIG.60. Thus, as in the case of the eighth embodiment, the data writeoperation can be conducted using the data write circuit 51 b having asimple structure.

[0667] Although the data write operation cannot be conducted based onthe folded bit line structure, the pitch of the write word lines WWL inthe memory array 10 can be widened. As a result, further improvedintegration of the memory array 10 and thus further reduced chip area ofthe MRAM device can be achieved.

[0668] Note that, although FIG. 64 shows the structure in which thewrite word line WWL out of the signal wirings associated with the datawrite operation is shared between adjacent memory cells, it is alsopossible to share the write bit line WBL instead of the write word lineWWL. In this case, however, the write word line WWL cannot be shared,and must be provided in every memory cell column. Which of the wiringsshould be shared to widen the wiring pitch can be determined in view ofthe distance from the magnetic tunnel junction MTJ, and the like.

[0669] Fifth Modification of Eighth Embodiment

[0670] In the fifth modification of the eighth embodiment, the read wordline RWL is shared between adjacent memory cells, in addition to thefolded bit line structure of the third modification of the eighthembodiment.

[0671] Referring to FIG. 65, in the memory array according to the fifthmodification of the eighth embodiment, adjacent memory cells in thecolumn direction share the same read word line RWL.

[0672] The read/write control circuit 60 includes the equalizingtransistors 62, precharging transistors 64 and write bit line voltagecontrol transistors 65, which are arranged in the same manner as that ofthe third modification of the eighth embodiment.

[0673] In the data write operation, the write word line WWL isactivated. In each write bit line WBL, the memory cells are providedevery other write word line WWL. Moreover, the memory cells are arrangedalternately between every adjacent write bit lines WBL. Therefore, everyset of adjacent two memory cell rows can form a write bit line pair. Asa result, the data write operation can be conducted based on the foldedbit line structure in the same manner as that of the third modificationof the eighth embodiment, so that the same effects can be obtained.

[0674] On the other hand, in the data read operation, the read word lineRWL shared by a plurality of memory cell rows is activated. Therefore,the data read operation cannot be conducted based on the folded bit linestructure. Accordingly, in the fifth modification of the eighthembodiment, the peripheral circuitry associated with selection of theread bit line RBL is arranged in the same manner as that shown in FIG.60.

[0675] With such a structure, the read operation margin based on thefolded bit line structure cannot be ensured, but the pitch of the readword lines RWL in the memory array 10 can be widened, and the data readoperation can be conducted normally. As a result, improved integrationof the memory array 10 and thus reduced chip area of the MRAM device canbe achieved.

[0676] Accordingly, by conducting the data write operation based on thefolded bit line structure using the memory cells of the eighthembodiment, the write operation margin can be ensured as well as asimplified structure of the peripheral circuitry and reduced data writenoise can be achieved. Moreover, by sharing the read word line RWL,improved integration of the memory array 10 can also be achievedsimultaneously.

[0677] Note that, although FIG. 65 shows the structure in which the readword line RWL out of the signal wirings associated with the data readoperation is shared between adjacent memory cells, it is also possibleto share the read bit line RBL instead of the read word line RWL. Inthis case, however, the read word line RWL cannot be shared, and must beprovided in every memory cell row. Which of the wirings should be sharedto widen the wiring pitch can be determined as appropriate in view ofthe structural conditions, design and the like.

[0678] Ninth Embodiment

[0679] Referring to FIG. 66, in the MTJ memory cell according to theninth embodiment, the access transistor ATR is electrically coupledbetween the magnetic tunnel junction MTJ and the write bit line WBL. Themagnetic tunnel junction MTJ is coupled between the access transistorATR and a common line CML. The access transistor ATR has its gatecoupled to the read word line RWL. In the structure of FIG. 66 as well,the common line CML serving as a write word line WWL and the read wordline RWL extend perpendicularly to each other. Therefore, the respectivedrive circuits for the common line CML and the read word line RWL can beseparately provided, whereby the freedom of layout design can beimproved.

[0680]FIG. 67 is a timing chart illustrating the data write and readoperations to and from the MTJ memory cell according to the ninthembodiment.

[0681] Referring to FIG. 67, in the data write operation, the data writecurrent ±Iw is supplied to the write bit line WBL. Moreover, in responseto turning-ON of a current control transistor described below, the datawrite current Ip flows through the common line CML corresponding to theselected column, according to the column selection result. Thus, thevoltage and current on the common line CML in the data write operationare set in the same manner as those of the write word line WWL shown inFIG. 33.

[0682] As a result, the magnetic field corresponding to the level of thewrite data DIN can be written to the magnetic tunnel junction MTJ.Moreover, as shown in FIG. 33, the read bit lines RBL are not requiredduring the data write operation. Therefore, the respective functions ofthe read bit line RBL and the write word line WWL can be integrated intothe common line CML.

[0683] In the operation other than the data write operation, theaforementioned current control transistors are turned OFF. The commonlines CML are precharged to the ground voltage Vss before the data readoperation.

[0684] In the data read operation, the voltage level on the write bitlines WBL is set to the ground voltage level Vss. Moreover, the sensecurrent Is for the data read operation is supplied to the common lineCML. Accordingly, in the data read operation, the read word line RWL isactivated to the selected state (H level) so as to turn ON the accesstransistor ATR. Thus, the sense current Is can be supplied through thepath formed by the common line CML, magnetic tunnel junction MTJ, accesstransistor ATR, and write bit line WBL.

[0685] When the current path of the sense current Is is formed in theMTJ memory cell, a voltage change (rise) corresponding to the storagedata is produced on the common line CML.

[0686] It is now assumed in FIG. 67 that the fixed magnetic layer FL andthe free magnetic layer VL have the same magnetic field direction whenthe storage data level is “1”. In this case, the common line CML has asmall voltage change AV1 when the storage data is “1”, and has a voltagechange AV2 larger than AV1 when the storage data is “0”. The storagedata in the MTJ memory cell can be read by sensing the differencebetween the voltage changes AV1 and AV2 on the common line CML.

[0687] Moreover, as shown in FIG. 33, the write word lines WWL are notrequired during the data read operation. Therefore, the write word linesWWL and the read bit lines RBL can be integrated into the common linesCML.

[0688] Thus, the same data write and read operations can be conductedeven with the MTJ memory cell that uses the common line CML integratingthe respective functions of the write word line WWL and the read bitline RBL so as to reduce the number of wirings.

[0689] The precharge voltage of the common lines CML functioning as theread bit lines RBL in the data read operation is set to the same voltagelevel as that of the common lines CML in the data write operation, i.e.,the ground voltage Vss. As a result, a precharge operation inpreparation for the read data operation can be performed moreefficiently, whereby the data read operation speed can be increased.

[0690] Referring to FIG. 68, in the MTJ memory cell according to theninth embodiment, the write bit line WBL is provided in the first metalwiring layer M1, and the read word line RWL is provided in the samelayer as that of the gate 130 of the access transistor ATR. The writebit line WBL is electrically coupled to the source/drain region 110 ofthe access transistor ATR. The other source/drain region 120 is coupledto the magnetic tunnel junction MTJ through the metal wiring provided inthe first metal wiring layer M1, the barrier metal 140, and the metalfilm 150 provided in the contact hole.

[0691] The common line CML is provided in the second metal wiring layerM2 so as to be electrically coupled to the magnetic tunnel junction MTJ.Since the common line CML has both functions of the read bit line RBLand the write word line WWL, reduction in the number of wirings as wellas the number of metal wiring layers, and thus reduction in themanufacturing cost can be achieved in addition to the effects obtainedby the MTJ memory cell according to the sixth embodiment.

[0692] In the MTJ memory cell according to the ninth embodiment, thewrite bit line WBL is located farther from the magnetic tunnel junctionMTJ than is the common line CML functioning as write word line WWL.Therefore, in the MTJ memory cell of the ninth embodiment, a relativelylarge data write current must be applied to the write bit line WBL.

[0693] Referring to FIG. 69, in the memory array according to the ninthembodiment, the memory cells MC shown in FIG. 66 are arranged in rowsand columns. The read word lines RWL and the write bit lines WBL extendin the row direction. The common lines CML extend in the columndirection. Like the read word lines RWL and the like, the common linesCML are also generally denoted with CML, and a specific common line isdenoted with CML1, and the like.

[0694] Adjacent memory cells in the row direction share the same commonline CML.

[0695] For example, the memory cell group of the first and second memorycell columns shares the same common line CML1, and the memory cell groupof the third and fourth memory cell columns shares the same common lineCML2. In the following memory cell columns as well, the common lines CMLare arranged similarly.

[0696] If the data is to be read from or written to a plurality ofmemory cells MC of the same common line CML, data collision occurs.Accordingly, the memory cells MC are arranged alternately.

[0697] With such a structure, the pitch of the common lines CML in thememory array 10 can be widened. As a result, the memory cells MC can beefficiently arranged, whereby improved integration of the memory array10 as well as reduced chip area of the MRAM device can be achieved.

[0698] The peripheral circuitry for selectively supplying the sensecurrent, which is provided for the read bit lines RBL in FIG. 35, isprovided for the common lines CML.

[0699] Current control transistors are provided corresponding to therespective common lines CML. FIG. 69 exemplarily shows the currentcontrol transistors 41-1 and 41-2 respectively corresponding to thecommon lines CML1 and CML2. Hereinafter, the current control transistorsare generally denoted with 41.

[0700] The current control transistor 41 is provided between thecorresponding common line CML and the ground voltage Vss. In the datawrite operation in which the common line CML functions as a write wordline WWL, the current control transistor 41 is turned ON in response toactivation of the control signal WE, so that the write word line driver30 w can supply the data write current Ip to the common line CMLactivated to the selected state (power supply voltage Vcc).

[0701] As described in connection with FIG. 67, the common lines CML areprecharged to the ground voltage Vss before the data read operation.Therefore, the precharging transistors 44 can be omitted by making thecurrent control transistors 41 operate also in response to the bit lineprecharging signal BLPR.

[0702] Since the structure of the peripheral circuitry for selectivelysupplying the data write current to the write bit line WBL is the sameas that of FIG. 35, detailed description thereof will not be repeated.

[0703] First Modification of Ninth Embodiment

[0704] Referring to FIG. 70, in the memory array according to the firstmodification of the ninth embodiment, adjacent memory cells share thesame write bit line WBL. For example, the memory cell group of thesecond and third memory cell rows shares the same write bit line WBL2.In the following memory cell columns as well, the write bit lines WBLare arranged similarly.

[0705] In order to conduct the data write operation normally, aplurality of memory cells MC must not be present at the intersection ofthe same common line CML and the same write bit line WBL. Accordingly,the common line CML is provided in every column, and the memory cells MCare arranged alternately.

[0706] Since the structure of the peripheral circuitry associated withthe data read and write operations through the common line CML and writebit line WBL, as well as the memory cell operation in reading andwriting the data are the same as those of the ninth embodiment, detaileddescription thereof will not be repeated.

[0707] With such a structure, the pitch of the write bit lines WBL inthe memory array 10 can be widened. As a result, the memory cells MC canbe efficiently arranged, whereby improved integration of the memoryarray 10 as well as reduced chip area of the MRAM device can beachieved.

[0708] As described before, in the MTJ memory cell of the ninthembodiment, a relatively large data write current must be applied to thewrite bit line WBL. Accordingly, the write bit line WBL is sharedbetween adjacent memory cells so as to ensure the line pitch thereof. Asa result, the line width, i.e., the cross-sectional area, of the writebit line WBL is assured, so that the current density thereof can besuppressed. As a result, improved reliability of the MRAM device can beachieved. As described before, for the improved operation reliability,it is also effective to select a material of these wirings in view ofelectromigration resistance.

[0709] Second Modification of Ninth Embodiment

[0710] Referring to FIG. 71, in the memory array according to the secondmodification of the ninth embodiment, adjacent memory cells in thecolumn direction share the same read word line RWL. For example, thememory cell group of the first and second memory cell rows shares thesame read word line RWL1. In the following memory cell rows as well, theread word lines RWL are arranged similarly.

[0711] Moreover, adjacent memory cells in the column direction share thesame write bit line WBL. For example, the memory cell group of thesecond and third memory cell rows shares the same write bit line WBL2.In the following memory cell rows as well, the write bit lines WBL arearranged similarly.

[0712] In order to conduct the data read operation normally, a pluralityof memory cells MC selected by the same read word line RWL must not besimultaneously coupled to the same common line CML. Accordingly, thecommon line CML is provided in every memory cell column, and the memorycells MC are arranged alternately.

[0713] Since the structure is otherwise the same as that of the ninthembodiment, detailed description thereof will not be repeated.

[0714] With such a structure, the pitches of the read word lines RWL andwrite bit lines WBL in the memory array 10 can be widened. As a result,the memory cells MC can be efficiently arranged, whereby improvedintegration of the memory array 10 as well as reduced chip area of theMRAM device can be achieved.

[0715] Third Modification of Ninth Embodiment

[0716] Referring to FIG. 72, for the memory cells having the structureof the ninth embodiment and arranged in rows and columns, the folded bitline structure is realized in every set of adjacent two memory cellcolumns, using corresponding two common lines CML. For example, a dataline pair corresponding to a read bit line pair can be formed from thecommon lines CML1 and CML2 (/CML1) respectively corresponding to thefirst and second memory cell columns.

[0717] Similarly, the folded bit line structure is realized in every setof adjacent two memory cell rows, using corresponding two write bitlines WBL. For example, a write bit line pair can be formed from thewrite bit lines WBL1 and WBL2 (/WBL1) respectively corresponding to thefirst and second memory cell rows.

[0718] The structure of the peripheral circuitry for conducting rowselection from the write bit lines WBL and /WBL of the write bit linepairs and supplying the data write current ±Iw thereto is the same asthat shown in FIG. 39. Therefore, detailed description thereof will notbe repeated.

[0719] Moreover, provided that one of the common lines forming each dataline pair in the data read operation is generally denoted with CML andthe other is generally denoted with /CML, the peripheral circuitry forconducting column selection from the read bit lines RBL and /RBL in thestructure of FIG. 39 and supplying the sense current Is thereto isprovided corresponding to the common lines CML and /CML.

[0720] Accordingly, even when the memory cells according to the ninthembodiment are arranged in rows and columns, the data read and writeoperation margins can be ensured using the folded bit line structure.

[0721] Fourth Modification of Ninth Embodiment

[0722] In the fourth modification of the ninth embodiment, the write bitline WBL is shared between adjacent memory cells, in addition to thefolded bit line structure shown in the third modification of the ninthembodiment.

[0723] Referring to FIG. 73, in the memory array according to the fourthmodification of the ninth embodiment, adjacent memory cells in thecolumn direction share the same write bit line WBL.

[0724] In the read operation, the read word line RWL is activated. Ineach common line CML functioning as a read bit line RBL, the memorycells are provided every other read word line RWL. Moreover, the memorycells are arranged alternately between every adjacent common lines CML.Therefore, every set of adjacent two memory cell columns form a dataline pair, so that the data read operation can be conducted based on thefolded bit line structure in the same manner as that of the thirdmodification of the ninth embodiment.

[0725] On the other hand, the data write operation cannot be conductedbased on the folded bit line structure because the write bit line WBL isshared. Accordingly, in the fourth modification of the ninth embodiment,the peripheral circuitry associated with selection of the write bit lineWBL is arranged in the same manner as that shown in FIG. 69. Thus, as inthe ninth embodiment, the data write operation can be conducted usingthe data write circuit 51 b having a simple structure.

[0726] Although the data write operation cannot be conducted based onthe folded bit line structure, the pitch of the write word lines WWL inthe memory array 10 can be widened. As a result, further improvedintegration of the memory array 10 and thus further reduced chip area ofthe MRAM device can be achieved.

[0727] Fifth Modification of Ninth Embodiment

[0728] In the fifth modification of the ninth embodiment, the read wordline RWL is shared between adjacent memory cells, in addition to thefolded bit line structure of the third modification of the ninthembodiment.

[0729] Referring to FIG. 74, in the memory array according to the fifthmodification of the ninth embodiment, adjacent memory cells in thecolumn direction share the same read word line RWL.

[0730] The read/write control circuit 60 includes the equalizingtransistors 62 and the write bit line voltage control transistors 65,which are arranged in the same manner as that of the third modificationof the ninth embodiment.

[0731] In each write bit line WBL, the memory cells are provided everyother common line CML. Moreover, the memory cells are arrangedalternately between every adjacent write bit lines WBL. Therefore, inthe data write operation, every set of adjacent two memory cell rows canform a write bit line pair. As a result, the data write operation can beconducted based on the folded bit line structure in the same manner asthat of the third modification of the ninth embodiment, so that the sameeffects can be obtained.

[0732] On the other hand, in the data read operation, the read word lineRWL shared by a plurality of memory cell rows is activated. Therefore,the data read operation cannot be conducted based on the folded bit linestructure. Accordingly, in the fifth modification of the ninthembodiment, the peripheral circuitry associated with selection of thecommon line CML functioning as a read bit line RBL is arranged in thesame manner as that shown in FIG. 69.

[0733] With such a structure, the read operation margin based on thefolded bit line structure cannot be ensured, but the pitch of the readword lines RWL in the memory array 10 can be widened, and the data readoperation can be conducted normally. As a result, improved integrationof the memory array 10 and thus reduced chip area of the MRAM device canbe achieved.

[0734] Accordingly, by conducting the data write operation based on thefolded bit line structure using the memory cells of the ninthembodiment, the write operation margin can be ensured as well as asimplified structure of the peripheral circuitry and reduced data writenoise can be achieved. Moreover, by sharing the read word line RWL,improved integration of the memory array 10 can also be achievedsimultaneously.

[0735] Tenth Embodiment

[0736] Referring to FIG. 75, in the MTJ memory cell according to thetenth embodiment, the access transistor ATR is coupled between thecommon line CML and the magnetic tunnel junction MTJ. The read word lineRWL is coupled to the gate of the access transistor ATR. The write bitline WBL extends in the same direction as that of the read word lineRWL, and is electrically coupled to the magnetic tunnel junction MTJ.

[0737] In the data write operation, like the write word line WWL, thecommon line CML is selectively activated by the write word line driver30 w. In the data read operation, the sense current Is is supplied tothe common line CML.

[0738] In the data write operation, in response to turning-ON of thecurrent control transistor 41-1 to 41-m, the data write current Ip flowsthrough the common line CML activated to the selected state (H level),like the write word line WWL. In the data read operation, the currentcontrol transistor 41-1 to 41-m is turned OFF, whereby the sense currentIs flows through the path formed by the common line CML, magnetic tunneljunction MTJ, access transistor ATR and write bit line WBL (groundvoltage Vss). As a result, a voltage change corresponding to the storagedata of the magnetic tunnel junction MTJ is produced on the common lineCML, as described in connection with FIG. 67.

[0739] Thus, as in the ninth embodiment, the common line CML functionsas a write word line WWL in the data write operation and as a read bitline RBL in the data read operation, whereby the number of wirings canbe reduced.

[0740] Moreover, the read word line RWL and the common line CMLfunctioning as a write word line in the data write operation extendperpendicularly to each other. Therefore, the read word line driver 30 rand the write word line driver 30 w can be independently provided,whereby the same effects as those of the sixth embodiment can beobtained.

[0741] Referring to FIG. 76, in the MTJ memory cell according to thetenth embodiment, the common line CML is provided in the first metalwiring layer M1 so as to be electrically coupled to the source/drainregion 110 of the access transistor ATR. The read word line RWL isformed in the same layer as that of the gate 130 of the accesstransistor ATR.

[0742] The source/drain region 120 is coupled to the magnetic tunneljunction MTJ through the metal wiring formed in the first metal wiringlayer M1, the barrier metal 140, and the metal film 150 formed in thecontact hole. The write bit line WBL is provided in the second metalwiring layer M2 so as to be electrically coupled to the magnetic tunneljunction MTJ.

[0743] The common line CML and the magnetic tunnel junction MTJ arecoupled to each other through the access transistor ATR. Therefore, thecommon line CML is coupled to the magnetic tunnel junction MTJ only whenthe access transistor ATR is turned ON. As a result, the capacitance ofthe common line CML functioning as a read bit line RBL in the data readoperation is reduced, whereby the data read operation speed can furtherbe increased.

[0744] Note that, in the MTJ memory cell of the tenth embodiment, thevoltage and current waveforms of each wiring in the data read and writeoperations are the same as those of the ninth embodiment. Therefore,detailed description thereof will not be repeated.

[0745] In the MTJ memory cell of the tenth embodiment, the common lineCML functioning as a write word line WWL is located farther from themagnetic tunnel junction MTJ than is the write bit line WBL. Therefore,in the MTJ memory cell of the tenth embodiment, a relatively large datawrite current must be applied to the common line CML.

[0746] Referring to FIG. 77, in the memory array according to the tenthembodiment, the memory cells MC shown in FIG. 75 are arranged in rowsand columns.

[0747] The read word lines RWL and the write bit lines WBL extend in therow direction. The common lines CML extend in the column direction.

[0748] Adjacent memory cells in the row direction share the same commonline CML.

[0749] For example, the memory cell group of the first and second memorycell columns shares the same common line CML1, and the memory cell groupof the third and fourth memory cell columns shares the same common lineCML2. In the following memory cell columns as well, the common lines CMLare arranged similarly.

[0750] If the data is to be read from or written to a plurality ofmemory cells MC of the same common line CML, data collision occurs.Accordingly, the memory cells MC are arranged alternately.

[0751] With such a structure, the pitch of the common lines CML in thememory array 10 can be widened. As a result, the memory cells MC can beefficiently arranged, whereby improved integration of the memory array10 as well as reduced chip area of the MRAM device can be achieved.

[0752] Since the structure of the peripheral circuitry for selectivelysupplying the data write current to the common line CML and the writebit line WBL is the same as that of FIG. 69, detailed descriptionthereof will not be repeated.

[0753] As described before, in the MTJ memory cell of the tenthembodiment, a relatively large data write current must be applied to thecommon line CML. Accordingly, the common line CML is shared betweenadjacent memory cells so as to ensure the line pitch thereof. As aresult, the line width, i.e., the cross-sectional area, of the commonline CML is assured, so that the current density thereof can besuppressed. Thus, improved reliability of the MRAM device can beachieved. As described before, for the improved operation reliability,it is also effective to select a material of these wirings in view ofelectromigration resistance.

[0754] First Modification of Tenth Embodiment

[0755] Referring to FIG. 78, in the memory array according to the firstmodification of the tenth embodiment, adjacent memory cells share thesame write bit line WBL. For example, the memory cell group of thesecond and third memory cell rows shares the same write bit line WBL2.In the following memory cell rows as well, the write bit lines WBL arearranged similarly.

[0756] In order to conduct the data write operation normally, aplurality of memory cells MC must not be present at the intersection ofthe same common line CML and the same write bit line WBL. Accordingly,the common line CML is provided in every column, and the memory cells MCare arranged alternately.

[0757] Since the structure of the peripheral circuitry associated withthe data read and write operations through the common line CML and writebit line WBL, as well as the memory cell operation in reading andwriting the data are the same as those of the tenth embodiment, detaileddescription thereof will not be repeated.

[0758] With such a structure, the pitch of the write bit lines WBL inthe memory array 10 can be widened. As a result, the memory cells MC canbe efficiently arranged, whereby improved integration of the memoryarray 10 as well as reduced chip area of the MRAM device can beachieved.

[0759] Second Modification of Tenth Embodiment

[0760] Referring to FIG. 79, in the memory array according to the secondmodification of the tenth embodiment, adjacent memory cells in thecolumn direction share the same read word line RWL. For example, thememory cell group of the first and second memory cell rows shares thesame read word line RWL1. In the following memory cell rows as well, theread word lines RWL are arranged similarly.

[0761] Moreover, adjacent memory cells in the column direction share thesame write bit line WBL. For example, the memory cell group of thesecond and third memory cell rows shares the same write bit line WBL2.In the following memory cell rows as well, the write bit lines WBL arearranged similarly.

[0762] In order to conduct the data read operation normally, a pluralityof memory cells MC selected by the same read word line RWL must not besimultaneously coupled to the same common line CML. Accordingly, thecommon line CML is provided in every memory cell column, and the memorycells MC are arranged alternately.

[0763] Since the structure is otherwise the same as that of the tenthembodiment, detailed description thereof will not be repeated.

[0764] With such a structure, the pitches of the read word lines RWL andwrite bit lines WBL in the memory array 10 can be widened. As a result,the memory cells MC can be efficiently arranged, whereby improvedintegration of the memory array 10 as well as reduced chip area of theMRAM device can be achieved.

[0765] Third Modification of Tenth Embodiment

[0766] Referring to FIG. 80, for the memory cells having the structureof the tenth embodiment and arranged in rows and columns, the folded bitline structure is realized in every set of adjacent two memory cellcolumns, using corresponding two common lines CML. For example, a dataline pair corresponding to a read bit line pair can be formed from thecommon lines CML1 and CML2 (/CML1) respectively corresponding to thefirst and second memory cell columns.

[0767] Similarly, the folded bit line structure is realized in every setof adjacent two memory cell rows, using corresponding two write bitlines WBL. For example, a write bit line pair can be formed from thewrite bit lines WBL1 and WBL2 (/WBL1) respectively corresponding to thefirst and second memory cell rows.

[0768] The structure of the peripheral circuitry for conducting rowselection from the write bit lines WBL and /WBL of the write bit linepairs and supplying the data write current ±Iw thereto is the same asthat shown in FIG. 72. Therefore, detailed description thereof will notbe repeated.

[0769] Similarly, the structure of the peripheral circuitry forconducting column selection from the common lines CML and /CML formingthe data line pairs in the data read operation, and supplying the sensecurrent Is thereto is the same as that shown in FIG. 72. Therefore,detailed description thereof will not be repeated.

[0770] Accordingly, even when the memory cells according to the tenthembodiment are arranged in rows and columns, the data read and writeoperation margins can be ensured using the folded bit line structure.

[0771] Fourth Modification of Tenth Embodiment

[0772] In the fourth modification of the tenth embodiment, the write bitline WBL is shared between adjacent memory cells, in addition to thefolded bit line structure shown in the third modification of the tenthembodiment.

[0773] Referring to FIG. 81, in the memory array according to the fourthmodification of the tenth embodiment, adjacent memory cells in thecolumn direction share the same write bit line WBL.

[0774] In the read operation, the read word line RWL is activated. Ineach common line CML functioning as a read bit line RBL, the memorycells are provided every other read word line RWL. Moreover, the memorycells are arranged alternately between every adjacent common lines CML.Therefore, every set of adjacent two memory cell columns form a dataline pair, so that the data read operation can be conducted based on thefolded bit line structure in the same manner as that of the thirdmodification of the tenth embodiment.

[0775] On the other hand, the data write operation cannot be conductedbased on the folded bit line structure because the write bit line WBL isshared. Accordingly, in the fourth modification of the tenth embodiment,the peripheral circuitry associated with selection of the write bit lineWBL is arranged in the same manner as that shown in FIG. 77. Thus, as inthe tenth embodiment, the data write operation can be conducted usingthe data write circuit 51 b having a simple structure.

[0776] Although the data write operation cannot be conducted based onthe folded bit line structure, the pitch of the write word lines WWL inthe memory array 10 can be widened. As a result, further improvedintegration of the memory array 10 and thus further reduced chip area ofthe MRAM device can be achieved.

[0777] Fifth Modification of Tenth Embodiment

[0778] In the fifth modification of the tenth embodiment, the read wordline RWL is shared between adjacent memory cells, in addition to thefolded bit line structure of the third modification of the tenthembodiment.

[0779] Referring to FIG. 82, in the memory array according to the fifthmodification of the tenth embodiment, adjacent memory cells in thecolumn direction share the same read word line RWL. The read/writecontrol circuit 60 includes the equalizing transistors 62 and the writebit line voltage control transistors 65, which are arranged in the samemanner as that of the third modification of the tenth embodiment.

[0780] In each write bit line WBL, the memory cells are provided everyother common line CML. Moreover, the memory cells are arrangedalternately between every adjacent write bit lines WBL. Therefore, inthe data write operation, every set of adjacent two memory cell rows canform a write bit line pair. As a result, the data write operation can beconducted based on the folded bit line structure in the same manner asthat of the third modification of the tenth embodiment, so that the sameeffects can be obtained.

[0781] On the other hand, in the data read operation, the read word lineRWL shared by a plurality of memory cell rows is activated. Therefore,the data read operation cannot be conducted based on the folded bit linestructure. Accordingly, in the fifth modification of the tenthembodiment, the peripheral circuitry associated with selection of thecommon line CML functioning as a read bit line RBL is arranged in thesame manner as that shown in FIG. 69.

[0782] With such a structure, the read operation margin based on thefolded bit line structure cannot be ensured, but the pitch of the readword lines RWL in the memory array 10 can be widened, and the data readoperation can be conducted normally. As a result, improved integrationof the memory array 10 and thus reduced chip area of the MRAM device canbe achieved.

[0783] Accordingly, by conducting the data write operation based on thefolded bit line structure using the memory cells of the tenthembodiment, the write operation margin can be ensured as well as asimplified structure of the peripheral circuitry and reduced data writenoise can be achieved. Moreover, by sharing the read word line RWL,improved integration of the memory array 10 can also be achievedsimultaneously.

[0784] Although the present invention has been described and illustratedin detail, it is clearly understood that the same is by way ofillustration and example only and is not to be taken by way oflimitation, the split and scope of the present invention being limitedonly by the terms of the appended claims.

1-15 (Cancelled).
 16. A thin film magnetic memory device, comprising: amemory array including a plurality of magnetic memory cells arranged inrows and columns, each of said plurality of magnetic memory cellsincluding a magnetic storage portion having a different resistance valueaccording to a level of storage data written when a data write magneticfield applied by first and second data write currents is larger than apredetermined magnetic field; a plurality of read word lines providedcorresponding to the respective rows of the magnetic memory cells, anddriven to a first voltage according to an address selection result in adata read operation; a plurality of write word lines providedcorresponding to the respective rows, and selectively activatedaccording the address selection result so as to pass said first datawrite current therethrough in a data write operation; and a plurality ofbit lines provided corresponding to the respective columns of themagnetic memory cells so as to extend in such a direction thatintersects said plurality of write word lines, and each coupled to thecorresponding magnetic storage portions, wherein one of said pluralityof bit lines that is selected according to the address selection resultpasses therethrough a data read current and said second data writecurrent in the data read operation and the data write operation,respectively, and each of said magnetic memory cells further includes arectifying access element connected between the corresponding magneticstorage portion and a corresponding one of said plurality of read wordlines.
 17. The thin film magnetic memory device according to claim 16,wherein adjacent magnetic memory cells share one of said plurality ofwrite word lines.
 18. The thin film magnetic memory device according toclaim 16, wherein each said write word lines has a largercross-sectional area than that of each said bit lines.
 19. The thin filmmagnetic memory device according to claim 16, wherein said plurality ofwrite word lines are formed from a material having higherelectromigration resistance than that of said plurality of bit lines.20. A thin film magnetic memory device, comprising: a memory arrayincluding a plurality of magnetic memory cells arranged in rows andcolumns, each of said plurality of magnetic memory cells including amagnetic storage portion having a different resistance value accordingto a level of storage data written when a data write magnetic fieldapplied by first and second data write currents is larger than apredetermined magnetic field; a plurality of word lines providedcorresponding to the respective rows of the magnetic memory cells, andeach shared between corresponding adjacent magnetic memory cells in thecolumn direction, wherein one of said plurality of word lines that isselected according to an address selection result is activated so as topass therethrough said first data write current and a data read currentin a data write operation and a data read operation, respectively; and aplurality of bit lines provided corresponding to the respective columnsof the magnetic memory cells so as to extend in such a direction thatcrosses said plurality of write word lines, and each coupled to thecorresponding magnetic storage portions, wherein one of said pluralityof bit lines that is selected according to the address selection resultpasses therethrough said data read current and said second data writecurrent in the data read operation and the data write operation,respectively, and each of said magnetic memory cells further includes arectifying access element connected between the corresponding magneticstorage portion and a corresponding one of said plurality of word lines.21. The thin film magnetic memory device according to claim 20, whereineach said word line has a larger cross-sectional area than that of eachsaid bit line.
 22. The thin film magnetic memory device according toclaim 20, wherein said plurality of word lines are formed from amaterial having higher electromigration resistance than that of saidplurality of bit lines.